On Wed, 26 Jun 2013 17:44:15 +0300 [email protected] wrote: > From: Ville Syrjälä <[email protected]> > > The DPLL lock bit, and the DPIO phy status bits are read-only and > controlled by the hardware, so they will never be set by the driver. > Mask them out when reading the hw state, so that the state > comparison won't fail. > > Signed-off-by: Ville Syrjälä <[email protected]> > --- > drivers/gpu/drm/i915/intel_display.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index 259ea4b..d67a9f5 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -4958,6 +4958,10 @@ static bool i9xx_get_pipe_config(struct intel_crtc > *crtc, > if (!IS_VALLEYVIEW(dev)) { > pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); > pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); > + } else { > + pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | > + DPLL_PORTC_READY_MASK | > + DPLL_PORTB_READY_MASK); > } > > return true;
As a rule I'd like to see comments explaining this too, so we don't have to dig through the changelog to figure it out. But that's no biggie here, so: Reviewed-by: Jesse Barnes <[email protected]> -- Jesse Barnes, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
