On Thu, 2020-03-05 at 12:24 -0800, Matt Roper wrote: > The UNSLICE_UNIT_LEVEL_CLKGATE and UNSLICE_UNIT_LEVEL_CLKGATE2 > registers > that we update in a few engine workarounds are not masked registers > (i.e., we don't have to write a mask bit in the top 16 bits when > updating one of the lower 16 bits). As such, these workarounds > should > be applied via wa_write_or() rather than wa_masked_en()
Thanks Nick for spotting and Matt for fixing it, did not notice this difference up to know. Reviewed-by: José Roberto de Souza <[email protected]> > > Reported-by: Nick Desaulniers <[email protected]> > Fixes: 50148a25f841 ("drm/i915/tgl: Move and restrict Wa_1408615072") > Fixes: 3551ff928744 ("drm/i915/gen11: Moving WAs to > rcs_engine_wa_init()") > Cc: José Roberto de Souza <[email protected]> > Signed-off-by: Matt Roper <[email protected]> > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c > b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 908a70914399..b4785212fb7d 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -1382,8 +1382,8 @@ rcs_engine_wa_init(struct intel_engine_cs > *engine, struct i915_wa_list *wal) > wa_masked_en(wal, GEN9_ROW_CHICKEN4, > GEN12_DISABLE_TDL_PUSH); > > /* Wa_1408615072:tgl */ > - wa_masked_en(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, > - VSUNIT_CLKGATE_DIS_TGL); > + wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, > + VSUNIT_CLKGATE_DIS_TGL); > } > > if (IS_TIGERLAKE(i915)) { > @@ -1467,12 +1467,12 @@ rcs_engine_wa_init(struct intel_engine_cs > *engine, struct i915_wa_list *wal) > * Wa_1408615072:icl,ehl (vsunit) > * Wa_1407596294:icl,ehl (hsunit) > */ > - wa_masked_en(wal, UNSLICE_UNIT_LEVEL_CLKGATE, > - VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS); > + wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, > + VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS); > > /* Wa_1407352427:icl,ehl */ > - wa_masked_en(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, > - PSDUNIT_CLKGATE_DIS); > + wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, > + PSDUNIT_CLKGATE_DIS); > > /* Wa_1406680159:icl,ehl */ > wa_write_or(wal, _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
