Chris Wilson <[email protected]> writes: > The residual w/a batch is casing system instablity on Ivybridge and > Baytrail under some workloads, so disable until resolved. > > Closes: https://gitlab.freedesktop.org/drm/intel/issues/1405 > Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts") > Signed-off-by: Chris Wilson <[email protected]> > Cc: Mika Kuoppala <[email protected]> > Cc: Prathap Kumar Valsan <[email protected]> > Cc: Akeem G Abodunrin <[email protected]> > Cc: Jani Nikula <[email protected]> > Cc: Joonas Lahtinen <[email protected]> > Cc: Rodrigo Vivi <[email protected]>
Acked-by: Mika Kuoppala <[email protected]> > --- > drivers/gpu/drm/i915/gt/intel_ring_submission.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c > b/drivers/gpu/drm/i915/gt/intel_ring_submission.c > index 1424582e4a9b..fdc3f10e12aa 100644 > --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c > +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c > @@ -2088,7 +2088,7 @@ int intel_ring_submission_setup(struct intel_engine_cs > *engine) > > GEM_BUG_ON(timeline->hwsp_ggtt != engine->status_page.vma); > > - if (IS_GEN(engine->i915, 7) && engine->class == RENDER_CLASS) { > + if (IS_HASWELL(engine->i915) && engine->class == RENDER_CLASS) { > err = gen7_ctx_switch_bb_init(engine); > if (err) > goto err_ring_unpin; > -- > 2.20.1 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
