On Fri, 2020-03-13 at 18:48 +0200, Ville Syrjala wrote: > From: Ville Syrjälä <[email protected]> > > Currently only port sync pipes do the sequence such that > we first do the modeset part for every pipe and then do > the plane/etc. updates. Let's follow that apporach for > all pipes in skl+ so that we can properly integrate the > port sync into the normal modeset flow. >
Reviewed-by: José Roberto de Souza <[email protected]> > Signed-off-by: Ville Syrjälä <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_display.c | 44 ++++++++++------ > ---- > 1 file changed, 22 insertions(+), 22 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > b/drivers/gpu/drm/i915/display/intel_display.c > index 33f38c8a5da4..3926ac8f1f10 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -15152,17 +15152,6 @@ static void > intel_update_trans_port_sync_crtcs(struct intel_atomic_state *state, > > usleep_range(200, 400); > intel_set_dp_tp_ctl_normal(state, crtc); > - > - for_each_new_intel_crtc_in_state(state, slave_crtc, > - new_slave_crtc_state, i) { > - if (new_slave_crtc_state->master_transcoder != > - new_crtc_state->cpu_transcoder) > - continue; > - > - intel_update_crtc(state, slave_crtc); > - } > - > - intel_update_crtc(state, crtc); > } > > static void icl_dbuf_slice_pre_update(struct intel_atomic_state > *state) > @@ -15251,6 +15240,8 @@ static void skl_commit_modeset_enables(struct > intel_atomic_state *state) > } > } > > + update_pipes = modeset_pipes; > + > /* > * Enable all pipes that needs a modeset and do not depends on > other > * pipes > @@ -15266,10 +15257,6 @@ static void > skl_commit_modeset_enables(struct intel_atomic_state *state) > is_trans_port_sync_slave(new_crtc_state)) > continue; > > - drm_WARN_ON(&dev_priv->drm, > skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, > - > entries, I915_MAX_PIPES, pipe)); > - > - entries[pipe] = new_crtc_state->wm.skl.ddb; > modeset_pipes &= ~BIT(pipe); > > if (is_trans_port_sync_mode(new_crtc_state)) { > @@ -15287,14 +15274,13 @@ static void > skl_commit_modeset_enables(struct intel_atomic_state *state) > } > } else { > intel_enable_crtc(state, crtc); > - intel_update_crtc(state, crtc); > } > } > > /* > - * Finally enable all pipes that needs a modeset and depends on > - * other pipes, right now it is only MST slaves as both port > sync slave > - * and master are enabled together > + * Then we enable all remaining pipes that depend on other > + * pipes, right now it is only MST slaves as both port sync > + * slave and master are enabled together > */ > for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, > i) { > enum pipe pipe = crtc->pipe; > @@ -15302,18 +15288,32 @@ static void > skl_commit_modeset_enables(struct intel_atomic_state *state) > if ((modeset_pipes & BIT(pipe)) == 0) > continue; > > + modeset_pipes &= ~BIT(pipe); > + > + intel_enable_crtc(state, crtc); > + } > + > + /* > + * Finally we do the plane updates/etc. for all pipes that got > enabled. > + */ > + for_each_oldnew_intel_crtc_in_state(state, crtc, > old_crtc_state, > + new_crtc_state, i) { > + enum pipe pipe = crtc->pipe; > + > + if ((update_pipes & BIT(pipe)) == 0) > + continue; > + > drm_WARN_ON(&dev_priv->drm, > skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, > > entries, I915_MAX_PIPES, pipe)); > > entries[pipe] = new_crtc_state->wm.skl.ddb; > - modeset_pipes &= ~BIT(pipe); > + update_pipes &= ~BIT(pipe); > > - intel_enable_crtc(state, crtc); > intel_update_crtc(state, crtc); > } > > drm_WARN_ON(&dev_priv->drm, modeset_pipes); > - > + drm_WARN_ON(&dev_priv->drm, update_pipes); > } > > static void intel_atomic_helper_free_state(struct drm_i915_private > *dev_priv) _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
