We always set it to the same value, so there is no need to actually have a variable for it and we can just use the value directly.
Signed-off-by: Daniele Ceraolo Spurio <[email protected]> Cc: Michal Wajdeczko <[email protected]> Cc: John Harrison <[email protected]> Cc: Matthew Brost <[email protected]> --- drivers/gpu/drm/i915/gt/intel_gt_types.h | 2 -- drivers/gpu/drm/i915/gt/uc/intel_guc.c | 8 ++++---- drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h | 3 +++ drivers/gpu/drm/i915/i915_irq.c | 4 ---- 4 files changed, 7 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h index 96890dd12b5f..81691cf1d411 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@ -85,8 +85,6 @@ struct intel_gt { u32 pm_ier; u32 pm_imr; - u32 pm_guc_events; - struct intel_engine_cs *engine[I915_NUM_ENGINES]; struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1] [MAX_ENGINE_INSTANCE + 1]; diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c index 5134d544bf4c..eadea9d47e31 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c @@ -85,7 +85,7 @@ static void gen9_reset_guc_interrupts(struct intel_guc *guc) assert_rpm_wakelock_held(>->i915->runtime_pm); spin_lock_irq(>->irq_lock); - gen6_gt_pm_reset_iir(gt, gt->pm_guc_events); + gen6_gt_pm_reset_iir(gt, GEN9_GUC_INTR_BIT(GUC2HOST)); spin_unlock_irq(>->irq_lock); } @@ -98,9 +98,9 @@ static void gen9_enable_guc_interrupts(struct intel_guc *guc) spin_lock_irq(>->irq_lock); if (!guc->interrupts.enabled) { WARN_ON_ONCE(intel_uncore_read(gt->uncore, GEN8_GT_IIR(2)) & - gt->pm_guc_events); + GEN9_GUC_INTR_BIT(GUC2HOST)); guc->interrupts.enabled = true; - gen6_gt_pm_enable_irq(gt, gt->pm_guc_events); + gen6_gt_pm_enable_irq(gt, GEN9_GUC_INTR_BIT(GUC2HOST)); } spin_unlock_irq(>->irq_lock); } @@ -114,7 +114,7 @@ static void gen9_disable_guc_interrupts(struct intel_guc *guc) spin_lock_irq(>->irq_lock); guc->interrupts.enabled = false; - gen6_gt_pm_disable_irq(gt, gt->pm_guc_events); + gen6_gt_pm_disable_irq(gt, GEN9_GUC_INTR_BIT(GUC2HOST)); spin_unlock_irq(>->irq_lock); intel_synchronize_irq(gt->i915); diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h index 1949346e714e..ae785a757316 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h @@ -143,4 +143,7 @@ struct guc_doorbell_info { #define GUC_INTR_SW_INT_1 BIT(1) #define GUC_INTR_SW_INT_0 BIT(0) +/* pre-gen11 the guc irqs bits are in the upper 16 bits of the pm reg */ +#define GEN9_GUC_INTR_BIT(x) (GUC_INTR_##x << 16) + #endif diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 1502ab44f1a5..a224a05b0551 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -3942,10 +3942,6 @@ void intel_irq_init(struct drm_i915_private *dev_priv) for (i = 0; i < MAX_L3_SLICES; ++i) dev_priv->l3_parity.remap_info[i] = NULL; - /* pre-gen11 the guc irqs bits are in the upper 16 bits of the pm reg */ - if (HAS_GT_UC(dev_priv) && INTEL_GEN(dev_priv) < 11) - dev_priv->gt.pm_guc_events = GUC_INTR_GUC2HOST << 16; - dev->vblank_disable_immediate = true; /* Most platforms treat the display irq block as an always-on -- 2.24.1 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
