Lionel Landwerlin <lionel.g.landwer...@intel.com> writes:
> On 05/05/2020 03:09, D Scott Phillips wrote:
>> D Scott Phillips <d.scott.phill...@intel.com> writes:
>>
>>> Previously we set HDC_PIPELINE_FLUSH in dword 1 of gen12
>>> pipe_control commands. HDC Pipeline flush actually resides in
>>> dword 0, and the bit we were setting in dword 1 was Indirect State
>>> Pointers Disable, which invalidates indirect state in the render
>>> context. This causes failures for userspace, as things like push
>>> constant state gets invalidated.
>>>
>>> Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com>
>>> Cc: Chris Wilson <ch...@chris-wilson.co.uk>
>>> Signed-off-by: D Scott Phillips <d.scott.phill...@intel.com>
>> also,
>>
>> Fixes: 4aa0b5d457f5 ("drm/i915/tgl: Add HDC Pipeline Flush")
>> _______________________________________________
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>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> I think Mika sent the same patch in "drm/i915/gen12: Fix HDC pipeline
> flush".
>
> -Lionel
Ah, quite right, I missed it. Ignore this.
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