Introduce platform dependent SAGV checking in
combination with bandwidth state pipe SAGV mask.

This is preparation to adding TGL support, which
requires different way of SAGV checking.

v2, v3, v4, v5, v6: Fix rebase conflict

v7: - Nuke icl specific function, use skl
      for icl as well, gen specific active_pipes
      check to be added in the next patch(Ville)

Signed-off-by: Stanislav Lisovskiy <[email protected]>
---
 drivers/gpu/drm/i915/intel_pm.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8a86298962dc..3dc1ad66beb3 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3804,7 +3804,7 @@ void intel_sagv_post_plane_update(struct 
intel_atomic_state *state)
                intel_enable_sagv(dev_priv);
 }
 
-static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state 
*crtc_state)
+static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
 {
        struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -3865,7 +3865,7 @@ static int intel_compute_sagv_mask(struct 
intel_atomic_state *state)
 {
        int ret;
        struct intel_crtc *crtc;
-       struct intel_crtc_state *new_crtc_state;
+       const struct intel_crtc_state *new_crtc_state;
        struct intel_bw_state *new_bw_state = NULL;
        const struct intel_bw_state *old_bw_state = NULL;
        int i;
@@ -3878,7 +3878,7 @@ static int intel_compute_sagv_mask(struct 
intel_atomic_state *state)
 
                old_bw_state = intel_atomic_get_old_bw_state(state);
 
-               if (intel_crtc_can_enable_sagv(new_crtc_state))
+               if (skl_crtc_can_enable_sagv(new_crtc_state))
                        new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
                else
                        new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
@@ -3889,6 +3889,7 @@ static int intel_compute_sagv_mask(struct 
intel_atomic_state *state)
 
        new_bw_state->active_pipes =
                intel_calc_active_pipes(state, old_bw_state->active_pipes);
+
        if (new_bw_state->active_pipes != old_bw_state->active_pipes) {
                ret = intel_atomic_lock_global_state(&new_bw_state->base);
                if (ret)
-- 
2.24.1.485.gad05a3d8e5

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