Although RKL is a gen12 platform, it doesn't have the two extra
instances of the ABOX control register; we should only program
the single MBUS_ABOX_CTL on this platform.

Note that the bspec tagging for this is a bit misleading/inconsistent;
the details that ABOX1/2 don't exist exists in the bspec, but is tagged
in a strange limbo state such that it doesn't take effect when a RKL
filter view is applied; we've confirmed experimentally that these two
extra register instances don't exist on the platform (and trigger
unclaimed register errors when accessed).

v2:
 - Store the mask of platform-specific abox registers in the device
   info structure.

Bspec: 50096
Bspec: 49218
Cc: Ville Syrjälä <[email protected]>
Signed-off-by: Matt Roper <[email protected]>
---
 drivers/gpu/drm/i915/display/intel_display_power.c | 10 ++++------
 drivers/gpu/drm/i915/i915_pci.c                    |  3 +++
 drivers/gpu/drm/i915/i915_reg.h                    |  9 ++++++---
 drivers/gpu/drm/i915/intel_device_info.h           |  1 +
 4 files changed, 14 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c 
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 5a324d5c9fe4..a2b9f1fe3bc7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4760,7 +4760,8 @@ static void gen9_dbuf_disable(struct drm_i915_private 
*dev_priv)
 
 static void icl_mbus_init(struct drm_i915_private *dev_priv)
 {
-       u32 mask, val;
+       unsigned long abox_regs = INTEL_INFO(dev_priv)->abox_mask;
+       u32 mask, val, i;
 
        mask = MBUS_ABOX_BT_CREDIT_POOL1_MASK |
                MBUS_ABOX_BT_CREDIT_POOL2_MASK |
@@ -4771,11 +4772,8 @@ static void icl_mbus_init(struct drm_i915_private 
*dev_priv)
                MBUS_ABOX_B_CREDIT(1) |
                MBUS_ABOX_BW_CREDIT(1);
 
-       intel_de_rmw(dev_priv, MBUS_ABOX_CTL, mask, val);
-       if (INTEL_GEN(dev_priv) >= 12) {
-               intel_de_rmw(dev_priv, MBUS_ABOX1_CTL, mask, val);
-               intel_de_rmw(dev_priv, MBUS_ABOX2_CTL, mask, val);
-       }
+       for_each_set_bit(i, &abox_regs, sizeof(abox_regs))
+               intel_de_rmw(dev_priv, MBUS_ABOX_CTL(i), mask, val);
 }
 
 static void hsw_assert_cdclk(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 3f1ccd899f4b..49651f60113b 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -804,6 +804,7 @@ static const struct intel_device_info cnl_info = {
 #define GEN11_FEATURES \
        GEN10_FEATURES, \
        GEN11_DEFAULT_PAGE_SIZES, \
+       .abox_mask = BIT(0), \
        .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
                BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
                BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
@@ -848,6 +849,7 @@ static const struct intel_device_info ehl_info = {
        GEN11_FEATURES, \
        GEN(12), \
        .bw_buddy_mask = GENMASK(2, 1), \
+       .abox_mask = GENMASK(2, 0), \
        .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
        .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
                BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
@@ -884,6 +886,7 @@ static const struct intel_device_info rkl_info = {
        GEN12_FEATURES,
        PLATFORM(INTEL_ROCKETLAKE),
        .bw_buddy_mask = BIT(0),
+       .abox_mask = BIT(0),
        .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
        .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
                BIT(TRANSCODER_C),
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fe2aefc12141..4c3e822e1024 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2879,9 +2879,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define LM_FIFO_WATERMARK   0x0000001F
 #define MI_ARB_STATE   _MMIO(0x20e4) /* 915+ only */
 
-#define MBUS_ABOX_CTL                  _MMIO(0x45038)
-#define MBUS_ABOX1_CTL                 _MMIO(0x45048)
-#define MBUS_ABOX2_CTL                 _MMIO(0x4504C)
+#define _MBUS_ABOX0_CTL                        0x45038
+#define _MBUS_ABOX1_CTL                        0x45048
+#define _MBUS_ABOX2_CTL                        0x4504C
+#define MBUS_ABOX_CTL(x)               _MMIO(_PICK(x, _MBUS_ABOX0_CTL, \
+                                                   _MBUS_ABOX1_CTL, \
+                                                   _MBUS_ABOX2_CTL))
 #define MBUS_ABOX_BW_CREDIT_MASK       (3 << 20)
 #define MBUS_ABOX_BW_CREDIT(x)         ((x) << 20)
 #define MBUS_ABOX_B_CREDIT_MASK                (0xF << 16)
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h
index 73da4f1b8e2e..363f62e2d361 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -176,6 +176,7 @@ struct intel_device_info {
        u8 cpu_transcoder_mask;
 
        u8 bw_buddy_mask;
+       u8 abox_mask;
 
 #define DEFINE_FLAG(name) u8 name:1
        DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
-- 
2.24.1

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