On Fri, 2020-06-05 at 03:23 +0300, Gwan-gyeong Mun wrote: > The IO buffer Wake and Fast Wake bit size and value have been changed from > Gen12+. > It programs default value of IO buffer Wake and Fast Wake on Gen12+. > > - Pre Gen12 > Bit location: IO buffer Wake: Register_PSR2_CTL[14:13] > Fast Wake: Register_PSR2_CTL[12:11] > > Value: 0x0: 8 lines > 0x1: 7 lines > 0x2: 6 lines > 0x3: 5 lines > > - Gen12+ > Bit location: IO buffer Wake: Register_PSR2_CTL[15:13] > Fast Wake: Register_PSR2_CTL[12:10] > > Value: 0x0: 5 lines > 0x1: 6 lines > 0x2: 7 lines > 0x3: 8 lines > 0x4: 9 lines > 0x5: 10 lines > 0x6: 11 lines > 0x7: 12 lines
If you define the macro like bellow you don't need to add this information to the commit description. > > Cc: José Roberto de Souza <[email protected]> > Signed-off-by: Gwan-gyeong Mun <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_psr.c | 19 +++++++++++++++++++ > drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ > 2 files changed, 25 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > b/drivers/gpu/drm/i915/display/intel_psr.c > index b7a2c102648a..de2a17fe8860 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -518,6 +518,25 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) > else > val |= EDP_PSR2_TP2_TIME_2500us; > > + if (INTEL_GEN(dev_priv) >= 12) { > + /* > + * TODO: In order to setting an optimal power consumption, > + * lower than 4k resoluition mode needs to decrese > IO_BUFFER_WAKE > + * and FAST_WAKE. And higher than 4K resolution mode needs > + * to increase IO_BUFFER_WAKE and FAST_WAKE. > + */ > + u32 io_buffer_wake = 0x2; /* default BSpec value, 7 lines */ > + u32 fast_wake = 0x2; /* default BSpec value, 7 lines */ > + > + /* > + * To program line 9 to 12 on IO_BUFFER_WAKE and FAST_WAKE, > + * EDP_PSR2_CTL should be set EDP_PSR2_BLOCK_COUNT_NUM_3. > + */ > + val |= EDP_PSR2_BLOCK_COUNT_NUM_2; > + val |= EDP_PSR2_IO_BUFFER_WAKE(io_buffer_wake); > + val |= EDP_PSR2_FAST_WAKE(fast_wake); The parameter for this 2 macros should be the number of the lines not the bit value. As you are at it, please set the GEN9+ default values, the TGL macros will need a "TGL_" prefix. > + > /* > * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is > * recommending keep this bit unset while PSR2 is enabled. > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 96d351fbeebb..d055b7d93a5d 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -4514,10 +4514,16 @@ enum { > #define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran, _PSR2_CTL_A) > #define EDP_PSR2_ENABLE (1 << 31) > #define EDP_SU_TRACK_ENABLE (1 << 30) > +#define EDP_PSR2_BLOCK_COUNT_NUM_2 (0 << 28) /* TGL+ */ > +#define EDP_PSR2_BLOCK_COUNT_NUM_3 (1 << 28) /* TGL+ */ > #define EDP_Y_COORDINATE_VALID (1 << 26) /* GLK and CNL+ */ > #define EDP_Y_COORDINATE_ENABLE (1 << 25) /* GLK and CNL+ */ > #define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20) > #define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20) > +#define EDP_PSR2_IO_BUFFER_WAKE(a) ((a) << 13) > +#define EDP_PSR2_IO_BUFFER_WAKE_MASK (0x7 << 13) /* TGL+ */ > +#define EDP_PSR2_FAST_WAKE(a) ((a) << 10) /* TGL+ */ > +#define EDP_PSR2_FAST_WAKE_MASK (0x7 << 10) /* TGL+ */ > #define EDP_PSR2_TP2_TIME_500us (0 << 8) > #define EDP_PSR2_TP2_TIME_100us (1 << 8) > #define EDP_PSR2_TP2_TIME_2500us (2 << 8) _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
