On Mon, 08 Jun 2020, Stanislav Lisovskiy <[email protected]> wrote: > This reverts commit 82ea174dc5425d4e85e25d0c4ba961a2e494392a. >
Please explain why. What's going on, why we need the revert. It's fine to reply here, the commit message can be amended by whoever applies the patch. BR, Jani. > Signed-off-by: Stanislav Lisovskiy <[email protected]> > Fixes: cd1915460861 ("drm/i915: Adjust CDCLK accordingly to our DBuf bw > needs") > --- > drivers/gpu/drm/i915/display/intel_cdclk.c | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c > b/drivers/gpu/drm/i915/display/intel_cdclk.c > index 08468b121d02..45f7f33d1144 100644 > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > @@ -2071,6 +2071,18 @@ int intel_crtc_compute_min_cdclk(const struct > intel_crtc_state *crtc_state) > /* Account for additional needs from the planes */ > min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk); > > + /* > + * HACK. Currently for TGL platforms we calculate > + * min_cdclk initially based on pixel_rate divided > + * by 2, accounting for also plane requirements, > + * however in some cases the lowest possible CDCLK > + * doesn't work and causing the underruns. > + * Explicitly stating here that this seems to be currently > + * rather a Hack, than final solution. > + */ > + if (IS_TIGERLAKE(dev_priv)) > + min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate); > + > if (min_cdclk > dev_priv->max_cdclk_freq) { > drm_dbg_kms(&dev_priv->drm, > "required cdclk (%d kHz) exceeds max (%d kHz)\n", -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
