From: Clinton A Taylor <[email protected]> HPD pins are inverted for DG1 platform.
Bspec: 49956 Cc: José Roberto de Souza <[email protected]> Cc: Matt Roper <[email protected]> Signed-off-by: Clinton A Taylor <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> --- drivers/gpu/drm/i915/i915_irq.c | 4 ++++ drivers/gpu/drm/i915/i915_reg.h | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index e8bdc52c94bb..6225390edbb4 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -3181,6 +3181,10 @@ static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv) static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv) { + intel_de_rmw(dev_priv, SOUTH_CHICKEN1, 0, + INVERT_DDIA_HPD | INVERT_DDIB_HPD | + INVERT_DDIC_HPD | INVERT_DDID_HPD); + icp_hpd_irq_setup(dev_priv, SDE_DDI_MASK_DG1, 0, DG1_DDI_HPD_ENABLE_MASK, 0); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 6a853088a6e2..6b5dee1a82e1 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8687,6 +8687,10 @@ enum { #define SOUTH_CHICKEN1 _MMIO(0xc2000) #define FDIA_PHASE_SYNC_SHIFT_OVR 19 #define FDIA_PHASE_SYNC_SHIFT_EN 18 +#define INVERT_DDID_HPD (1 << 18) +#define INVERT_DDIC_HPD (1 << 17) +#define INVERT_DDIB_HPD (1 << 16) +#define INVERT_DDIA_HPD (1 << 15) #define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) #define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) #define FDI_BC_BIFURCATION_SELECT (1 << 12) -- 2.26.2 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
