On Thu, Jul 02, 2020 at 12:15:26PM +0300, Stanislav Lisovskiy wrote: > We still need "Bump up CDCLK" workaround otherwise getting > underruns - however currently it blocks 8K as CDCLK = Pixel rate, > in 8K case would require CDCLK to be around 1 Ghz which is not > possible. > > v2: - Convert to expression(max(min_cdclk, min(pixel_rate, max_cdclk)) > (Ville Syrjälä) > - Use type specific min_t, max_t(Ville Syrjälä) > > Signed-off-by: Stanislav Lisovskiy <[email protected]>
I have tested this and this unblocks 8K Reviewed-by: Manasi Navare <[email protected]> Manasi > --- > drivers/gpu/drm/i915/display/intel_cdclk.c | 11 +++++++++-- > 1 file changed, 9 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c > b/drivers/gpu/drm/i915/display/intel_cdclk.c > index 45f7f33d1144..8f9320e1e249 100644 > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > @@ -2080,8 +2080,15 @@ int intel_crtc_compute_min_cdclk(const struct > intel_crtc_state *crtc_state) > * Explicitly stating here that this seems to be currently > * rather a Hack, than final solution. > */ > - if (IS_TIGERLAKE(dev_priv)) > - min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate); > + if (IS_TIGERLAKE(dev_priv)) { > + /* > + * Clamp to max_cdclk_freq in case pixel rate is higher, > + * in order not to break an 8K, but still leave W/A at place. > + */ > + min_cdclk = max_t(int, min_cdclk, > + min_t(int, crtc_state->pixel_rate, > + dev_priv->max_cdclk_freq)); > + } > > if (min_cdclk > dev_priv->max_cdclk_freq) { > drm_dbg_kms(&dev_priv->drm, > -- > 2.24.1.485.gad05a3d8e5 > _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
