Myriadx code has it set to these values.
v2: upclassed dev_private
Signed-off-by: Anitha Chrisanthus <anitha.chrisant...@intel.com>
Reviewed-by: Bob Paauwe <bob.j.paa...@intel.com>
---
drivers/gpu/drm/kmb/kmb_crtc.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/kmb_crtc.c
index 5c1e858..eca0f3a 100644
--- a/drivers/gpu/drm/kmb/kmb_crtc.c
+++ b/drivers/gpu/drm/kmb/kmb_crtc.c
@@ -102,6 +102,9 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc)
kmb_write_lcd(dev_p, LCD_H_BACKPORCH, vm.hback_porch - 1);
kmb_write_lcd(dev_p, LCD_H_FRONTPORCH, vm.hfront_porch - 1);
kmb_write_lcd(dev_p, LCD_HSYNC_WIDTH, vm.hsync_len - 1);
+ /*this is hardcoded as 0 in the Myriadx code */
+ kmb_write_lcd(dev_p, LCD_VSYNC_START, 0);
+ kmb_write_lcd(dev_p, LCD_VSYNC_END, 0);
if (m->flags == DRM_MODE_FLAG_INTERLACE) {
kmb_write_lcd(dev_p,
@@ -112,10 +115,9 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc)
LCD_V_FRONTPORCH_EVEN, vm.vfront_porch - 1);
kmb_write_lcd(dev_p,
LCD_V_ACTIVEHEIGHT_EVEN, m->crtc_vdisplay - 1);
- kmb_write_lcd(dev_p, LCD_VSYNC_START_EVEN,
- vsync_start_offset);
- kmb_write_lcd(dev_p, LCD_VSYNC_END_EVEN,
- vsync_end_offset);
+ /*this is hardcoded as 10 in the Myriadx code*/
+ kmb_write_lcd(dev_p, LCD_VSYNC_START_EVEN, 10);
+ kmb_write_lcd(dev_p, LCD_VSYNC_END_EVEN, 10);
}
/* enable VL1 layer as default */
ctrl = LCD_CTRL_ENABLE | LCD_CTRL_VL1_ENABLE;
--
2.7.4
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