On Thu, 30 Jul 2020 at 17:52, Chris Wilson <ch...@chris-wilson.co.uk> wrote: > > We may need to allocate more than one pinned context/timeline for each > engine which can utilise the per-engine HWSP, so we need to give each > a different offset within it. > > Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.a...@intel.com> _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
- [Intel-gfx] [PATCH] drm/i915/gt: Support multiple pinned time... Chris Wilson
- Re: [Intel-gfx] [PATCH] drm/i915/gt: Support multiple pi... Chris Wilson
- [Intel-gfx] [PATCH] drm/i915/gt: Support multiple pinned... Chris Wilson
- Re: [Intel-gfx] [PATCH] drm/i915/gt: Support multipl... Matthew Auld
- [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/gt: Sup... Patchwork
- [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Suppor... Patchwork
- [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/gt: Sup... Patchwork
- [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Suppor... Patchwork