From: Paulo Zanoni <[email protected]> Same thing as INTEL_IRQ_REG_RESET, but now on a separate patch, as requested by Ben.
Signed-off-by: Paulo Zanoni <[email protected]> --- drivers/gpu/drm/i915/i915_irq.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 9684f1e..7588ad3 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -79,6 +79,15 @@ static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */ [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS }; +#define INTEL_IRQ_REG_RESET16(type, do_iir) do { \ + I915_WRITE16(type##MR, 0xffff); \ + I915_WRITE16(type##ER, 0); \ + if (do_iir) \ + I915_WRITE16(type##IR, I915_READ16(type##IR)); \ + else \ + POSTING_READ16(type##ER); \ +} while (0) + #define INTEL_IRQ_REG_RESET(type) do { \ I915_WRITE(type##MR, 0xffffffff); \ I915_WRITE(type##ER, 0); \ @@ -2308,9 +2317,7 @@ static void i8xx_irq_preinstall(struct drm_device * dev) for_each_pipe(pipe) I915_WRITE(PIPESTAT(pipe), 0); - I915_WRITE16(IMR, 0xffff); - I915_WRITE16(IER, 0x0); - POSTING_READ16(IER); + INTEL_IRQ_REG_RESET16(I, false); } static int i8xx_irq_postinstall(struct drm_device *dev) @@ -2448,9 +2455,7 @@ static void i8xx_irq_uninstall(struct drm_device * dev) I915_WRITE(PIPESTAT(pipe), 0); I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); } - I915_WRITE16(IMR, 0xffff); - I915_WRITE16(IER, 0x0); - I915_WRITE16(IIR, I915_READ16(IIR)); + INTEL_IRQ_REG_RESET16(I, true); } static void i915_irq_preinstall(struct drm_device * dev) -- 1.8.1.2 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
