On Thu, Jul 25, 2013 at 7:27 PM, Jesse Barnes <jbar...@virtuousgeek.org> wrote:
> On Thu, 25 Jul 2013 18:17:59 +0100
> Chris Wilson <ch...@chris-wilson.co.uk> wrote:
>
>> On Thu, Jul 25, 2013 at 10:06:50AM -0700, Jesse Barnes wrote:
>> > Art confirms that this should work fine. Since most panels are 18bpp
>> > with dithering from 24bpp, the existing code wouldn't be enabled in most
>> > cases.
>> >
>> > Signed-off-by: Jesse Barnes <jbar...@virtuousgeek.org>
>> > ---
>> > drivers/gpu/drm/i915/intel_display.c | 2 +-
>> > 1 file changed, 1 insertion(+), 1 deletion(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/intel_display.c
>> > b/drivers/gpu/drm/i915/intel_display.c
>> > index 12ea1a9..7cf475b 100644
>> > --- a/drivers/gpu/drm/i915/intel_display.c
>> > +++ b/drivers/gpu/drm/i915/intel_display.c
>> > @@ -4091,7 +4091,7 @@ static void hsw_compute_ips_config(struct intel_crtc
>> > *crtc,
>> > {
>> > pipe_config->ips_enabled = i915_enable_ips &&
>> > hsw_crtc_supports_ips(crtc) &&
>> > - pipe_config->pipe_bpp == 24;
>> > + pipe_config->pipe_bpp <= 24;
>>
>> Don't you want to check that the incoming fb is depth 24?
>
> I think this field will have the right bits in it for a 12bpc HDMI
> config for example, so we should be able to use it for IPS support.
Atm the above should work, but I expect that longer-term we need to
track sprite/plane configuration bits (like the watermark stuff
maybe), too. Only HDMI rounds up from the fb bpp value, but it doesn't
round up 8bpc to 12bpc. This might change eventually when we get
around to implement the high-precision gamma tables, since with a
10bpc display it would make sense to have the higher precision even
with a 24bpp scanout buffer.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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