From: Ville Syrjälä <[email protected]> Rename ilk_pipe_wm to ilk_wm_state to match how things are named for g4x/vlv.
Signed-off-by: Ville Syrjälä <[email protected]> --- .../drm/i915/display/intel_display_types.h | 8 +++--- drivers/gpu/drm/i915/intel_pm.c | 28 +++++++++---------- 2 files changed, 18 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 6b31af60d24d..9b4be062a7ef 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -672,7 +672,7 @@ struct ilk_wm_level { u16 fbc_val; }; -struct ilk_pipe_wm { +struct ilk_wm_state { struct ilk_wm_level wm[5]; bool fbc_wm_enabled; bool pipe_enabled; @@ -745,13 +745,13 @@ struct intel_crtc_wm_state { * switching away from and the new * configuration we're switching to. */ - struct ilk_pipe_wm intermediate; + struct ilk_wm_state intermediate; /* * Optimal watermarks, programmed post-vblank * when this state is committed. */ - struct ilk_pipe_wm optimal; + struct ilk_wm_state optimal; } ilk; struct { @@ -1147,7 +1147,7 @@ struct intel_crtc { struct { /* watermarks currently being used */ union { - struct ilk_pipe_wm ilk; + struct ilk_wm_state ilk; struct vlv_wm_state vlv; struct g4x_wm_state g4x; } active; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 871d374fb93f..61bb36239930 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3114,7 +3114,7 @@ static void skl_setup_wm_latency(struct drm_i915_private *dev_priv) } static bool ilk_validate_pipe_wm(const struct drm_i915_private *dev_priv, - struct ilk_pipe_wm *pipe_wm) + struct ilk_wm_state *pipe_wm) { /* LP0 watermark maximums depend on this pipe alone */ const struct ilk_wm_config config = { @@ -3141,7 +3141,7 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state) { struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct ilk_pipe_wm *pipe_wm; + struct ilk_wm_state *pipe_wm; struct intel_plane *plane; const struct intel_plane_state *plane_state; const struct intel_plane_state *pristate = NULL; @@ -3217,12 +3217,12 @@ static int ilk_compute_intermediate_wm(struct intel_crtc_state *newstate) { struct intel_crtc *intel_crtc = to_intel_crtc(newstate->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); - struct ilk_pipe_wm *a = &newstate->wm.ilk.intermediate; + struct ilk_wm_state *a = &newstate->wm.ilk.intermediate; struct intel_atomic_state *intel_state = to_intel_atomic_state(newstate->uapi.state); const struct intel_crtc_state *oldstate = intel_atomic_get_old_crtc_state(intel_state, intel_crtc); - const struct ilk_pipe_wm *b = &oldstate->wm.ilk.optimal; + const struct ilk_wm_state *b = &oldstate->wm.ilk.optimal; int level, max_level = ilk_wm_max_level(dev_priv); /* @@ -3281,7 +3281,7 @@ static void ilk_merge_wm_level(struct drm_i915_private *dev_priv, ret_wm->enable = true; for_each_intel_crtc(&dev_priv->drm, intel_crtc) { - const struct ilk_pipe_wm *active = &intel_crtc->wm.active.ilk; + const struct ilk_wm_state *active = &intel_crtc->wm.active.ilk; const struct ilk_wm_level *wm = &active->wm[level]; if (!active->pipe_enabled) @@ -3308,7 +3308,7 @@ static void ilk_merge_wm_level(struct drm_i915_private *dev_priv, static void ilk_wm_merge(struct drm_i915_private *dev_priv, const struct ilk_wm_config *config, const struct ilk_wm_maximums *max, - struct ilk_pipe_wm *merged) + struct ilk_wm_state *merged) { int level, max_level = ilk_wm_max_level(dev_priv); int last_enabled_level = max_level; @@ -3360,7 +3360,7 @@ static void ilk_wm_merge(struct drm_i915_private *dev_priv, } } -static int ilk_wm_lp_to_level(int wm_lp, const struct ilk_pipe_wm *pipe_wm) +static int ilk_wm_lp_to_level(int wm_lp, const struct ilk_wm_state *pipe_wm) { /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */ return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable); @@ -3377,7 +3377,7 @@ static unsigned int ilk_wm_lp_latency(struct drm_i915_private *dev_priv, } static void ilk_compute_wm_results(struct drm_i915_private *dev_priv, - const struct ilk_pipe_wm *merged, + const struct ilk_wm_state *merged, enum ilk_ddb_partitioning partitioning, struct ilk_wm_values *results) { @@ -3442,10 +3442,10 @@ static void ilk_compute_wm_results(struct drm_i915_private *dev_priv, /* Find the result with the highest level enabled. Check for enable_fbc_wm in * case both are at the same level. Prefer r1 in case they're the same. */ -static struct ilk_pipe_wm * +static struct ilk_wm_state * ilk_find_best_result(struct drm_i915_private *dev_priv, - struct ilk_pipe_wm *r1, - struct ilk_pipe_wm *r2) + struct ilk_wm_state *r1, + struct ilk_wm_state *r2) { int level, max_level = ilk_wm_max_level(dev_priv); int level1 = 0, level2 = 0; @@ -6140,7 +6140,7 @@ static void ilk_compute_wm_config(struct drm_i915_private *dev_priv, /* Compute the currently _active_ config */ for_each_intel_crtc(&dev_priv->drm, crtc) { - const struct ilk_pipe_wm *wm = &crtc->wm.active.ilk; + const struct ilk_wm_state *wm = &crtc->wm.active.ilk; if (!wm->pipe_enabled) continue; @@ -6153,7 +6153,7 @@ static void ilk_compute_wm_config(struct drm_i915_private *dev_priv, static void ilk_program_watermarks(struct drm_i915_private *dev_priv) { - struct ilk_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm; + struct ilk_wm_state lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm; struct ilk_wm_maximums max; struct ilk_wm_config config = {}; struct ilk_wm_values results = {}; @@ -6281,7 +6281,7 @@ static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc) struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct ilk_wm_values *hw = &dev_priv->wm.ilk; struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); - struct ilk_pipe_wm *active = &crtc_state->wm.ilk.optimal; + struct ilk_wm_state *active = &crtc_state->wm.ilk.optimal; enum pipe pipe = crtc->pipe; hw->wm_pipe[pipe] = I915_READ(WM0_PIPE_ILK(pipe)); -- 2.26.2 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
