Quoting Huang, Sean Z (2020-11-15 23:07:55) > Add several PXP-related reg into allowlist to allow > ring3 driver to read the those register values.
The individual registers need to be spelled out and their usage on the UMD side needs to be documented. There needs to be a link to the Open Source userspace which requires these registers. > Signed-off-by: Huang, Sean Z <[email protected]> <SNIP> > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -12419,4 +12419,12 @@ enum skl_power_gate { > #define TGL_ROOT_DEVICE_SKU_ULX 0x2 > #define TGL_ROOT_DEVICE_SKU_ULT 0x4 > > +/* Registers for passlist check */ > +#define PXP_REG_01_LOWERBOUND _MMIO(0x32260) > +#define PXP_REG_01_UPPERBOUND _MMIO(0x32268) > +#define PXP_REG_02_LOWERBOUND _MMIO(0x32670) > +#define PXP_REG_02_UPPERBOUND _MMIO(0x32678) > +#define PXP_REG_03_LOWERBOUND _MMIO(0x32860) > +#define PXP_REG_03_UPPERBOUND _MMIO(0x32c7c) This is not any more informative than embedding magical values in the code. Regards, Joonas _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
