On Tue, Nov 17, 2020 at 10:50:18AM -0800, Aditya Swarup wrote: > Initialize display outputs and add HTI support for ADL-S. ADL-S has 5 > display outputs -> 1 eDP, 2 HDMI and 2 DP++ outputs. > > Cc: Jani Nikula <[email protected]> > Cc: Ville Syrjälä <[email protected]> > Cc: Imre Deak <[email protected]> > Cc: Matt Roper <[email protected]> > Cc: Lucas De Marchi <[email protected]> > Signed-off-by: Aditya Swarup <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_display.c | 8 +++++++- > drivers/gpu/drm/i915/i915_pci.c | 1 + > drivers/gpu/drm/i915/i915_reg.h | 2 +- > 3 files changed, 9 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > b/drivers/gpu/drm/i915/display/intel_display.c > index dcb70efbfa3b..db8ba5e297ff 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -17261,7 +17261,13 @@ static void intel_setup_outputs(struct > drm_i915_private *dev_priv) > if (!HAS_DISPLAY(dev_priv)) > return; > > - if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) { > + if (IS_ALDERLAKE_S(dev_priv)) { > + intel_ddi_init(dev_priv, PORT_A); > + intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */ > + intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */ > + intel_ddi_init(dev_priv, PORT_F); /* DDI TC3 */ > + intel_ddi_init(dev_priv, PORT_G); /* DDI TC4 */ > + } else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) { > intel_ddi_init(dev_priv, PORT_A); > intel_ddi_init(dev_priv, PORT_B); > intel_ddi_init(dev_priv, PORT_TC1); > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c > index 069ac0c28bb3..26e4bf8bb4ef 100644 > --- a/drivers/gpu/drm/i915/i915_pci.c > +++ b/drivers/gpu/drm/i915/i915_pci.c > @@ -930,6 +930,7 @@ static const struct intel_device_info adl_s_info = { > PLATFORM(INTEL_ALDERLAKE_S), > .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), > .require_force_probe = 1, > + .display.has_hti = 1, > .display.has_psr_hw_tracking = 0, > .platform_engine_mask = > BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
This part should probably just go in the patch that added the initial platform definition. > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 5416d04373ae..4c8d0d84af6a 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -2928,7 +2928,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > #define MBUS_BBOX_CTL_S2 _MMIO(0x45044) > > #define HDPORT_STATE _MMIO(0x45050) > -#define HDPORT_DPLL_USED_MASK REG_GENMASK(14, 12) > +#define HDPORT_DPLL_USED_MASK REG_GENMASK(15, 12) This doesn't seem like it belongs in this patch. The DPLL patch might be a better match for it? Matt > #define HDPORT_PHY_USED_DP(phy) REG_BIT(2 * (phy) + 2) > #define HDPORT_PHY_USED_HDMI(phy) REG_BIT(2 * (phy) + 1) > #define HDPORT_ENABLED REG_BIT(0) > -- > 2.27.0 > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
