When defining OA formats for TGL, some formats were left out. Add them
back and clean up the uapi comments to reflect available formats.
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.rama...@intel.com>
---
drivers/gpu/drm/i915/i915_perf.c | 12 +++++-------
include/uapi/drm/i915_drm.h | 24 ++++++++++++++----------
2 files changed, 19 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index afa92cf075c4..659fcc9ae819 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -310,14 +310,12 @@ static const struct i915_oa_format
oa_formats[I915_OA_FORMAT_MAX] = {
[I915_OA_FORMAT_A45_B8_C8] = { 5, 256, INTEL_IVYBRIDGE,
INTEL_HASWELL },
[I915_OA_FORMAT_B4_C8_A16] = { 6, 128, INTEL_IVYBRIDGE,
INTEL_HASWELL },
- /* haswell+ upto but not including tigerlake */
- [I915_OA_FORMAT_C4_B8] = { 7, 64, INTEL_IVYBRIDGE,
INTEL_TIGERLAKE - 1 },
+ /* haswell+ */
+ [I915_OA_FORMAT_C4_B8] = { 7, 64, INTEL_HASWELL,
INTEL_MAX_PLATFORMS - 1 },
- /* gen8+ upto but not including tigerlake */
- [I915_OA_FORMAT_A12] = { 0, 64, INTEL_BROADWELL,
INTEL_TIGERLAKE - 1 },
- [I915_OA_FORMAT_A12_B8_C8] = { 2, 128, INTEL_BROADWELL,
INTEL_TIGERLAKE - 1 },
-
- /* gen8+ */
+ /* broadwell+ */
+ [I915_OA_FORMAT_A12] = { 0, 64, INTEL_BROADWELL,
INTEL_MAX_PLATFORMS - 1 },
+ [I915_OA_FORMAT_A12_B8_C8] = { 2, 128, INTEL_BROADWELL,
INTEL_MAX_PLATFORMS - 1 },
[I915_OA_FORMAT_A32u40_A4u32_B8_C8] = { 5, 256, INTEL_BROADWELL,
INTEL_MAX_PLATFORMS - 1 },
};
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 6edcb2b6c708..933511c2892e 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1951,20 +1951,24 @@ struct drm_i915_gem_userptr {
};
enum drm_i915_oa_format {
- I915_OA_FORMAT_A13 = 1, /* HSW only */
- I915_OA_FORMAT_A29, /* HSW only */
- I915_OA_FORMAT_A13_B8_C8, /* HSW only */
- I915_OA_FORMAT_B4_C8, /* HSW only */
- I915_OA_FORMAT_A45_B8_C8, /* HSW only */
- I915_OA_FORMAT_B4_C8_A16, /* HSW only */
- I915_OA_FORMAT_C4_B8, /* HSW+ */
-
- /* Gen8+ */
+ /* haswell */
+ I915_OA_FORMAT_A13 = 1,
+ I915_OA_FORMAT_A29,
+ I915_OA_FORMAT_A13_B8_C8,
+ I915_OA_FORMAT_B4_C8,
+ I915_OA_FORMAT_A45_B8_C8,
+ I915_OA_FORMAT_B4_C8_A16,
+
+ /* haswell+ */
+ I915_OA_FORMAT_C4_B8,
+
+ /* broadwell+ */
I915_OA_FORMAT_A12,
I915_OA_FORMAT_A12_B8_C8,
I915_OA_FORMAT_A32u40_A4u32_B8_C8,
- I915_OA_FORMAT_MAX /* non-ABI */
+ /* non-ABI */
+ I915_OA_FORMAT_MAX
};
enum drm_i915_perf_property_id {
--
2.20.1
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