From: Stuart Abercrombie <[email protected]> Higher dot clocks were working because pixel doubling was enabled.
Lower the apparently arbitrary threshold so it's enabled for 2048x1280. Intel hasn't felt moved to document any of this, so this is purely empirical. The original threshold was introduced here: http://cgit.freedesktop.org/~anholt/xf86-video-intel/commit/?id=8fcf9a81179ee8577ddab5e904c58fbfd14cf59c Change-Id: I1eff5db3f26fc2e7953edae9422047353f66f475 Reviewed-on: https://gerrit.chromium.org/gerrit/49896 Tested-by: Stuart Abercrombie <[email protected]> Reviewed-by: Stéphane Marchesin <[email protected]> Commit-Queue: Stuart Abercrombie <[email protected]> --- drivers/gpu/drm/i915/intel_display.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 7bd1d7a..349f019 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4805,14 +4805,14 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, dspcntr |= DISPPLANE_SEL_PIPE_B; if (pipe == 0 && INTEL_INFO(dev)->gen < 4) { - /* Enable pixel doubling when the dot clock is > 90% of the (display) + /* Enable pixel doubling when the dot clock is > 85% of the (display) * core speed. * * XXX: No double-wide on 915GM pipe B. Is that the only reason for the * pipe == 0 check? */ if (mode->clock > - dev_priv->display.get_display_clock_speed(dev) * 9 / 10) + dev_priv->display.get_display_clock_speed(dev) * 17 / 20) pipeconf |= PIPECONF_DOUBLE_WIDE; else pipeconf &= ~PIPECONF_DOUBLE_WIDE; -- 1.8.3.2 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
