From: CQ Tang <[email protected]> The lmem region needs to remove the stolen part, which should just be a case of snipping it off the end.
Signed-off-by: CQ Tang <[email protected]> Signed-off-by: Matthew Auld <[email protected]> --- drivers/gpu/drm/i915/gt/intel_region_lmem.c | 12 ++++++++---- drivers/gpu/drm/i915/i915_reg.h | 2 ++ 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c index bdd38efe0811..30959c1e535f 100644 --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c @@ -140,21 +140,24 @@ intel_setup_fake_lmem(struct drm_i915_private *i915) static struct intel_memory_region * setup_lmem(struct drm_i915_private *i915) { + struct intel_uncore *uncore = &i915->uncore; struct pci_dev *pdev = i915->drm.pdev; struct intel_memory_region *mem; resource_size_t io_start; - resource_size_t size; + resource_size_t lmem_size; /* Enables Local Memory functionality in GAM */ intel_uncore_write(&i915->uncore, GEN12_LMEM_CFG_ADDR, intel_uncore_read(&i915->uncore, GEN12_LMEM_CFG_ADDR) | LMEM_ENABLE); + /* Stolen starts from GSMBASE on DG1 */ + lmem_size = intel_uncore_read64(uncore, GEN12_GSMBASE); + io_start = pci_resource_start(pdev, 2); - size = pci_resource_len(pdev, 2); mem = intel_memory_region_create(i915, 0, - size, + lmem_size, I915_GTT_PAGE_SIZE_4K, io_start, &intel_region_lmem_ops); @@ -162,7 +165,8 @@ setup_lmem(struct drm_i915_private *i915) drm_dbg(&i915->drm, "Intel graphics LMEM: %pR\n", &mem->region); drm_dbg(&i915->drm, "Intel graphics LMEM IO start: %pa\n", &mem->io_start); - drm_info(&i915->drm, "Intel graphics LMEM size: %pa\n", &size); + drm_info(&i915->drm, "Intel graphics LMEM size: %pa\n", + &lmem_size); } return mem; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 28001b5a3cb5..626ebbe64bfd 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -12114,6 +12114,8 @@ enum skl_power_gate { #define GEN12_LMEM_CFG_ADDR _MMIO(0xcf58) #define LMEM_ENABLE (1 << 31) +#define GEN12_GSMBASE _MMIO(0x108100) + /* gamt regs */ #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4) #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */ -- 2.26.2 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
