Chris Wilson <[email protected]> writes: > Flush; invalidate; change registers; invalidate; flush. > > Will this finally work on every device? Or will Baytrail complain again? > > On the positive side, we immediate see the benefit of having hsw-gt1 in > CU. CI
Acked-by: Mika Kuoppala <[email protected]> > > Fixes: ace44e13e577 ("drm/i915/gt: Clear CACHE_MODE prior to clearing > residuals") > Testcase: igt/gem_render_tiled_blits # hsw-gt1 > Signed-off-by: Chris Wilson <[email protected]> > Cc: Mika Kuoppala <[email protected]> > Cc: Akeem G Abodunrin <[email protected]> > --- > drivers/gpu/drm/i915/gt/gen7_renderclear.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c > b/drivers/gpu/drm/i915/gt/gen7_renderclear.c > index 8551e6de50e8..e403eb046a43 100644 > --- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c > +++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c > @@ -393,6 +393,7 @@ static void emit_batch(struct i915_vma * const vma, > desc_count); > > /* Reset inherited context registers */ > + gen7_emit_pipeline_flush(&cmds); > gen7_emit_pipeline_invalidate(&cmds); > batch_add(&cmds, MI_LOAD_REGISTER_IMM(2)); > batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_0_GEN7)); > -- > 2.20.1 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
