From: CQ Tang <[email protected]> The lmem region needs to remove the stolen part, which should just be a case of snipping it off the end.
Signed-off-by: CQ Tang <[email protected]> Signed-off-by: Matthew Auld <[email protected]> --- drivers/gpu/drm/i915/gt/intel_region_lmem.c | 12 ++++++++---- drivers/gpu/drm/i915/i915_reg.h | 2 ++ 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c index b676dc67dc2a..4da808e35ecb 100644 --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c @@ -141,17 +141,20 @@ intel_gt_setup_fake_lmem(struct intel_gt *gt) static struct intel_memory_region *setup_lmem(struct intel_gt *gt) { struct drm_i915_private *i915 = gt->i915; + struct intel_uncore *uncore = &i915->uncore; struct pci_dev *pdev = i915->drm.pdev; struct intel_memory_region *mem; resource_size_t io_start; - resource_size_t size; + resource_size_t lmem_size; + + /* Stolen starts from GSMBASE on DG1 */ + lmem_size = intel_uncore_read64(uncore, GEN12_GSMBASE); io_start = pci_resource_start(pdev, 2); - size = pci_resource_len(pdev, 2); mem = intel_memory_region_create(i915, 0, - size, + lmem_size, I915_GTT_PAGE_SIZE_4K, io_start, &intel_region_lmem_ops); @@ -159,7 +162,8 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt) drm_dbg(&i915->drm, "Local memory: %pR\n", &mem->region); drm_dbg(&i915->drm, "Local memory IO start: %pa\n", &mem->io_start); - drm_info(&i915->drm, "Local memory available: %pa\n", &size); + drm_info(&i915->drm, "Local memory available: %pa\n", + &lmem_size); } return mem; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index d5719d1a2916..84897d1e5800 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -12118,6 +12118,8 @@ enum skl_power_gate { #define GEN12_GLOBAL_MOCS(i) _MMIO(0x4000 + (i) * 4) /* Global MOCS regs */ +#define GEN12_GSMBASE _MMIO(0x108100) + /* gamt regs */ #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4) #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */ -- 2.26.2 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
