Slice shutdown is a power savings feature whereby parts of HW i.e. slice is shut off on boot or dynamically to save power.
This patch only introduces a way to disable half of Haswell slices on boot. Dynamic shutdown is yet to be implemented. This gt_init already sets MI_PREDICATE_RESULT_2 appropriately. Signed-off-by: Rodrigo Vivi <[email protected]> --- drivers/gpu/drm/i915/i915_drv.c | 5 +++++ drivers/gpu/drm/i915/i915_drv.h | 3 +++ drivers/gpu/drm/i915/i915_reg.h | 16 ++++++++++++++++ drivers/gpu/drm/i915/intel_pm.c | 23 +++++++++++++++++++++++ 4 files changed, 47 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 735dd56..fe89bdc 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -154,6 +154,11 @@ module_param_named(prefault_disable, i915_prefault_disable, bool, 0600); MODULE_PARM_DESC(prefault_disable, "Disable page prefaulting for pread/pwrite/reloc (default:false). For developers only."); +int i915_slice_shutdown __read_mostly = 0; +module_param_named(slice_shutdown, i915_slice_shutdown, int, 0600); +MODULE_PARM_DESC(slice_shutdown, + "Disable half of EUs at boot time to save power."); + static struct drm_driver driver; extern int intel_agp_enabled; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 05de1ca..796aac7 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1595,6 +1595,8 @@ struct drm_i915_file_private { ((dev)->pci_device & 0xFF00) == 0x0C00) #define IS_ULT(dev) (IS_HASWELL(dev) && \ ((dev)->pci_device & 0xFF00) == 0x0A00) +#define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ + ((dev)->pci_device & 0x00F0) == 0x0020) /* * The genX designation typically refers to the render engine, so render @@ -1712,6 +1714,7 @@ extern bool i915_fastboot __read_mostly; extern int i915_enable_pc8 __read_mostly; extern int i915_pc8_timeout __read_mostly; extern bool i915_prefault_disable __read_mostly; +extern int i915_slice_shutdown __read_mostly; extern int i915_suspend(struct drm_device *dev, pm_message_t state); extern int i915_resume(struct drm_device *dev); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 8b81516..9ca93c4 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -278,6 +278,22 @@ #define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */ #define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */ #define MI_SEMAPHORE_SYNC_INVALID (3<<16) + +#define MI_PREDICATE_RESULT_2 (0x2214) +#define LOWER_SLICE_ENABLED (1<<0) +#define LOWER_SLICE_DISABLED (0<<0) + +#define HSW_GT_SLICE_INFO 0x138064 +#define SLICE_SEL_BOTH (1<<3) +#define SLICE_AUTOWAKE (1<<2) +#define SLICE_STATUS_MASK 0x3 +#define SLICE_STATUS_GT_OFF (0<<0) +#define SLICE_STATUS_MAIN_ON (2<<0) +#define SLICE_STATUS_BOTH_ON (3<<0) + +#define HSW_SLICESHUTDOWN 0xA190 +#define SLICE_SHUTDOWN (1<<0) + /* * 3D instructions used by the kernel */ diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 6b1d003..4301401 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3617,6 +3617,28 @@ static void gen6_enable_rps(struct drm_device *dev) gen6_gt_force_wake_put(dev_priv); } +static void intel_init_gt_slices(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + + if (!IS_HSW_GT3(dev)) + return; + + if (i915_slice_shutdown) { + I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_DISABLED); + POSTING_READ(MI_PREDICATE_RESULT_2); + + I915_WRITE(HSW_SLICESHUTDOWN, SLICE_SHUTDOWN); + POSTING_READ(HSW_SLICESHUTDOWN); + + I915_WRITE(HSW_GT_SLICE_INFO, ~SLICE_SEL_BOTH); + POSTING_READ(HSW_GT_SLICE_INFO); + } else { + I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_ENABLED); + POSTING_READ(MI_PREDICATE_RESULT_2); + } +} + void gen6_update_ring_freq(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -4630,6 +4652,7 @@ static void intel_gen6_powersave_work(struct work_struct *work) } else { gen6_enable_rps(dev); gen6_update_ring_freq(dev); + intel_init_gt_slices(dev); } mutex_unlock(&dev_priv->rps.hw_lock); } -- 1.8.1.4 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
