On Fri, May 07, 2021 at 07:27:42PM -0700, Matt Roper wrote: > From: Vandita Kulkarni <[email protected]> > > Support compression BPPs from bpc to uncompressed BPP -1. > So far we have 8,10,12 as valid compressed BPPS now the > support is extended. > > Cc: Manasi Navare <[email protected]> > Signed-off-by: Vandita Kulkarni <[email protected]> > Signed-off-by: Matt Roper <[email protected]>
Reviewed-by: Manasi Navare <[email protected]> Manasi > --- > drivers/gpu/drm/i915/display/intel_dp.c | 32 ++++++++++++++++++------- > 1 file changed, 24 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index f163a669f40f..8ccb3c3888f7 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -109,6 +109,7 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp) > } > > static void intel_dp_unset_edid(struct intel_dp *intel_dp); > +static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 > dsc_max_bpc); > > /* update sink rates from dpcd */ > static void intel_dp_set_sink_rates(struct intel_dp *intel_dp) > @@ -494,7 +495,8 @@ small_joiner_ram_size_bits(struct drm_i915_private *i915) > static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, > u32 link_clock, u32 lane_count, > u32 mode_clock, u32 mode_hdisplay, > - bool bigjoiner) > + bool bigjoiner, > + u32 pipe_bpp) > { > u32 bits_per_pixel, max_bpp_small_joiner_ram; > int i; > @@ -519,6 +521,7 @@ static u16 intel_dp_dsc_get_output_bpp(struct > drm_i915_private *i915, > drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n", > max_bpp_small_joiner_ram); > > + > /* > * Greatest allowed DSC BPP = MIN (output BPP from available Link BW > * check, output bpp from small joiner RAM check) > @@ -541,12 +544,17 @@ static u16 intel_dp_dsc_get_output_bpp(struct > drm_i915_private *i915, > return 0; > } > > - /* Find the nearest match in the array of known BPPs from VESA */ > - for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) { > - if (bits_per_pixel < valid_dsc_bpp[i + 1]) > - break; > + /* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs > */ > + if (DISPLAY_VER(i915) >= 13) { > + bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1); > + } else { > + /* Find the nearest match in the array of known BPPs from VESA > */ > + for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) { > + if (bits_per_pixel < valid_dsc_bpp[i + 1]) > + break; > + } > + bits_per_pixel = valid_dsc_bpp[i]; > } > - bits_per_pixel = valid_dsc_bpp[i]; > > /* > * Compressed BPP in U6.4 format so multiply by 16, for Gen 11, > @@ -780,6 +788,12 @@ intel_dp_mode_valid(struct drm_connector *connector, > */ > if (DISPLAY_VER(dev_priv) >= 10 && > drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) { > + /* > + * TBD pass the connector BPC, > + * for now U8_MAX so that max BPC on that platform would be > picked > + */ > + int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX); > + > if (intel_dp_is_edp(intel_dp)) { > dsc_max_output_bpp = > drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) > >> 4; > @@ -793,7 +807,8 @@ intel_dp_mode_valid(struct drm_connector *connector, > max_lanes, > target_clock, > mode->hdisplay, > - bigjoiner) >> 4; > + bigjoiner, > + pipe_bpp) >> 4; > dsc_slice_count = > intel_dp_dsc_get_slice_count(intel_dp, > target_clock, > @@ -1240,7 +1255,8 @@ static int intel_dp_dsc_compute_config(struct intel_dp > *intel_dp, > pipe_config->lane_count, > adjusted_mode->crtc_clock, > > adjusted_mode->crtc_hdisplay, > - pipe_config->bigjoiner); > + pipe_config->bigjoiner, > + pipe_bpp); > dsc_dp_slice_count = > intel_dp_dsc_get_slice_count(intel_dp, > adjusted_mode->crtc_clock, > -- > 2.25.4 > _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
