From: Ville Syrjälä <[email protected]> Rename the dkl phy buf trans tables to follow the same naming pattern used by everyone else.
v2: Handle adl-p Reviewed-by: Jani Nikula <[email protected]> #v1 Signed-off-by: Ville Syrjälä <[email protected]> --- .../drm/i915/display/intel_ddi_buf_trans.c | 32 +++++++++---------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c index 3f38267b7dd6..7f3c23d9c1da 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c @@ -605,7 +605,7 @@ static const union intel_ddi_buf_trans_entry icl_mg_phy_ddi_translations_hdmi[] { .mg = { 0x36, 0x0, 0x9 } }, /* 10 Full -3 dB */ }; -static const union intel_ddi_buf_trans_entry tgl_dkl_phy_dp_ddi_trans[] = { +static const union intel_ddi_buf_trans_entry tgl_dkl_phy_ddi_translations_dp_hbr[] = { /* VS pre-emp Non-trans mV Pre-emph dB */ { .dkl = { 0x7, 0x0, 0x00 } }, /* 0 0 400mV 0 dB */ { .dkl = { 0x5, 0x0, 0x05 } }, /* 0 1 400mV 3.5 dB */ @@ -619,7 +619,7 @@ static const union intel_ddi_buf_trans_entry tgl_dkl_phy_dp_ddi_trans[] = { { .dkl = { 0x0, 0x0, 0x00 } }, /* 3 0 1200mV 0 dB HDMI default */ }; -static const union intel_ddi_buf_trans_entry tgl_dkl_phy_dp_ddi_trans_hbr2[] = { +static const union intel_ddi_buf_trans_entry tgl_dkl_phy_ddi_translations_dp_hbr2[] = { /* VS pre-emp Non-trans mV Pre-emph dB */ { .dkl = { 0x7, 0x0, 0x00 } }, /* 0 0 400mV 0 dB */ { .dkl = { 0x5, 0x0, 0x05 } }, /* 0 1 400mV 3.5 dB */ @@ -633,7 +633,7 @@ static const union intel_ddi_buf_trans_entry tgl_dkl_phy_dp_ddi_trans_hbr2[] = { { .dkl = { 0x0, 0x0, 0x00 } }, /* 3 0 1200mV 0 dB HDMI default */ }; -static const union intel_ddi_buf_trans_entry tgl_dkl_phy_hdmi_ddi_trans[] = { +static const union intel_ddi_buf_trans_entry tgl_dkl_phy_ddi_translations_hdmi[] = { /* HDMI Preset VS Pre-emph */ { .dkl = { 0x7, 0x0, 0x0 } }, /* 1 400mV 0dB */ { .dkl = { 0x6, 0x0, 0x0 } }, /* 2 500mV 0dB */ @@ -734,7 +734,7 @@ static const union intel_ddi_buf_trans_entry rkl_combo_phy_ddi_translations_dp_h { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ }; -static const union intel_ddi_buf_trans_entry adlp_dkl_phy_dp_ddi_trans_hbr[] = { +static const union intel_ddi_buf_trans_entry adlp_dkl_phy_ddi_translations_dp_hbr[] = { /* VS pre-emp Non-trans mV Pre-emph dB */ { .dkl = { 0x7, 0x0, 0x01 } }, /* 0 0 400mV 0 dB */ { .dkl = { 0x5, 0x0, 0x06 } }, /* 0 1 400mV 3.5 dB */ @@ -748,7 +748,7 @@ static const union intel_ddi_buf_trans_entry adlp_dkl_phy_dp_ddi_trans_hbr[] = { { .dkl = { 0x0, 0x0, 0x00 } }, /* 3 0 1200mV 0 dB */ }; -static const union intel_ddi_buf_trans_entry adlp_dkl_phy_dp_ddi_trans_hbr2_hbr3[] = { +static const union intel_ddi_buf_trans_entry adlp_dkl_phy_ddi_translations_dp_hbr2_hbr3[] = { /* VS pre-emp Non-trans mV Pre-emph dB */ { .dkl = { 0x7, 0x0, 0x00 } }, /* 0 0 400mV 0 dB */ { .dkl = { 0x5, 0x0, 0x04 } }, /* 0 1 400mV 3.5 dB */ @@ -1363,8 +1363,8 @@ tgl_get_dkl_buf_trans_hdmi(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) { - *n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans); - return tgl_dkl_phy_hdmi_ddi_trans; + *n_entries = ARRAY_SIZE(tgl_dkl_phy_ddi_translations_hdmi); + return tgl_dkl_phy_ddi_translations_hdmi; } static const union intel_ddi_buf_trans_entry * @@ -1373,11 +1373,11 @@ tgl_get_dkl_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) { if (crtc_state->port_clock > 270000) { - *n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans_hbr2); - return tgl_dkl_phy_dp_ddi_trans_hbr2; + *n_entries = ARRAY_SIZE(tgl_dkl_phy_ddi_translations_dp_hbr2); + return tgl_dkl_phy_ddi_translations_dp_hbr2; } else { - *n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans); - return tgl_dkl_phy_dp_ddi_trans; + *n_entries = ARRAY_SIZE(tgl_dkl_phy_ddi_translations_dp_hbr); + return tgl_dkl_phy_ddi_translations_dp_hbr; } } @@ -1398,12 +1398,12 @@ adlp_get_dkl_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) { if (crtc_state->port_clock > 270000) { - *n_entries = ARRAY_SIZE(adlp_dkl_phy_dp_ddi_trans_hbr2_hbr3); - return adlp_dkl_phy_dp_ddi_trans_hbr2_hbr3; + *n_entries = ARRAY_SIZE(adlp_dkl_phy_ddi_translations_dp_hbr2_hbr3); + return adlp_dkl_phy_ddi_translations_dp_hbr2_hbr3; + } else { + *n_entries = ARRAY_SIZE(adlp_dkl_phy_ddi_translations_dp_hbr); + return adlp_dkl_phy_ddi_translations_dp_hbr; } - - *n_entries = ARRAY_SIZE(adlp_dkl_phy_dp_ddi_trans_hbr); - return adlp_dkl_phy_dp_ddi_trans_hbr; } const union intel_ddi_buf_trans_entry * -- 2.31.1 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
