[Intel-gfx] [PATCH] drm/i915/gen11: use ffs for minconfig slice/subslice

[Tejas Upadhyay]

w/a on gen11 platforms not working as expected and causing
more harm on the RC6 flow. Because of subslice steering
disturbance w/a read is failing. By using ffs we can default
steering of slice/sublice to minconfig hence w/a will pass
and any warns will go away.

Fixes: fb899dd8ea9c ("drm/i915: Apply Wa_1406680159:icl,ehl as an engine 
workaround")
Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com>
Cc: Matt Roper <matthew.d.ro...@intel.com>
Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadh...@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 14 +++++++++++---
 drivers/gpu/drm/i915/intel_pm.c             | 10 +++++++---
 2 files changed, 18 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index b62d1e31a645..68b14141088a 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -991,13 +991,21 @@ wa_init_mcr(struct drm_i915_private *i915, struct 
i915_wa_list *wal)
                l3_en = ~0;
        }
 
-       slice = fls(sseu->slice_mask) - 1;
-       subslice = fls(l3_en & intel_sseu_get_subslices(sseu, slice));
+       if (GRAPHICS_VER(i915) == 11) {
+               slice = ffs(sseu->slice_mask) - 1;
+               subslice = ffs(l3_en & intel_sseu_get_subslices(sseu, slice));
+       } else {
+               slice = fls(sseu->slice_mask) - 1;
+               subslice = fls(l3_en & intel_sseu_get_subslices(sseu, slice));
+       }
        if (!subslice) {
                drm_warn(&i915->drm,
                         "No common index found between subslice mask %x and L3 
bank mask %x!\n",
                         intel_sseu_get_subslices(sseu, slice), l3_en);
-               subslice = fls(l3_en);
+               if (GRAPHICS_VER(i915) == 11)
+                       subslice = ffs(l3_en);
+               else
+                       subslice = fls(l3_en);
                drm_WARN_ON(&i915->drm, !subslice);
        }
        subslice--;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 45fefa0ed160..d1352ec3546a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4049,9 +4049,13 @@ skl_ddb_entry_for_slices(struct drm_i915_private 
*dev_priv, u8 slice_mask,
                ddb->end = 0;
                return;
        }
-
-       ddb->start = (ffs(slice_mask) - 1) * slice_size;
-       ddb->end = fls(slice_mask) * slice_size;
+       if (GRAPHICS_VER(dev_priv) == 11) {
+               ddb->start = (fls(slice_mask) - 1) * slice_size;
+               ddb->end = ffs(slice_mask) * slice_size;
+       } else {
+               ddb->start = (ffs(slice_mask) - 1) * slice_size;
+               ddb->end = fls(slice_mask) * slice_size;
+       }
 
        WARN_ON(ddb->start >= ddb->end);
        WARN_ON(ddb->end > INTEL_INFO(dev_priv)->dbuf.size);
-- 
2.31.1

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