On Mon, Jun 14, 2021 at 08:34:31PM -0700, Matt Roper wrote: > From: Daniele Ceraolo Spurio <[email protected]> > > New steering cases will be added in the follow-up patches, so prepare a > common helper to avoid code duplication. > > Cc: Tvrtko Ursulin <[email protected]> > Signed-off-by: Daniele Ceraolo Spurio <[email protected]> > Signed-off-by: Matt Roper <[email protected]>
Reviewed-by: Rodrigo Vivi <[email protected]> > --- > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 41 +---------------- > drivers/gpu/drm/i915/intel_uncore.c | 55 +++++++++++++++++++++++ > drivers/gpu/drm/i915/intel_uncore.h | 6 +++ > 3 files changed, 63 insertions(+), 39 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c > b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > index 9ceddfbb1687..8b913c6961c3 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > @@ -1105,45 +1105,8 @@ static u32 > read_subslice_reg(const struct intel_engine_cs *engine, > int slice, int subslice, i915_reg_t reg) > { > - struct drm_i915_private *i915 = engine->i915; > - struct intel_uncore *uncore = engine->uncore; > - u32 mcr_mask, mcr_ss, mcr, old_mcr, val; > - enum forcewake_domains fw_domains; > - > - if (GRAPHICS_VER(i915) >= 11) { > - mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK; > - mcr_ss = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice); > - } else { > - mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK; > - mcr_ss = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice); > - } > - > - fw_domains = intel_uncore_forcewake_for_reg(uncore, reg, > - FW_REG_READ); > - fw_domains |= intel_uncore_forcewake_for_reg(uncore, > - GEN8_MCR_SELECTOR, > - FW_REG_READ | > FW_REG_WRITE); > - > - spin_lock_irq(&uncore->lock); > - intel_uncore_forcewake_get__locked(uncore, fw_domains); > - > - old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR); > - > - mcr &= ~mcr_mask; > - mcr |= mcr_ss; > - intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr); > - > - val = intel_uncore_read_fw(uncore, reg); > - > - mcr &= ~mcr_mask; > - mcr |= old_mcr & mcr_mask; > - > - intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr); > - > - intel_uncore_forcewake_put__locked(uncore, fw_domains); > - spin_unlock_irq(&uncore->lock); > - > - return val; > + return intel_uncore_read_with_mcr_steering(engine->uncore, reg, > + slice, subslice); > } > > /* NB: please notice the memset */ > diff --git a/drivers/gpu/drm/i915/intel_uncore.c > b/drivers/gpu/drm/i915/intel_uncore.c > index 1bed8f666048..d067524f9162 100644 > --- a/drivers/gpu/drm/i915/intel_uncore.c > +++ b/drivers/gpu/drm/i915/intel_uncore.c > @@ -2277,6 +2277,61 @@ intel_uncore_forcewake_for_reg(struct intel_uncore > *uncore, > return fw_domains; > } > > +u32 intel_uncore_read_with_mcr_steering_fw(struct intel_uncore *uncore, > + i915_reg_t reg, > + int slice, int subslice) > +{ > + u32 mcr_mask, mcr_ss, mcr, old_mcr, val; > + > + lockdep_assert_held(&uncore->lock); > + > + if (GRAPHICS_VER(uncore->i915) >= 11) { > + mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK; > + mcr_ss = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice); > + } else { > + mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK; > + mcr_ss = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice); > + } > + > + old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR); > + > + mcr &= ~mcr_mask; > + mcr |= mcr_ss; > + intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr); > + > + val = intel_uncore_read_fw(uncore, reg); > + > + mcr &= ~mcr_mask; > + mcr |= old_mcr & mcr_mask; > + > + intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr); > + > + return val; > +} > + > +u32 intel_uncore_read_with_mcr_steering(struct intel_uncore *uncore, > + i915_reg_t reg, int slice, int subslice) > +{ > + enum forcewake_domains fw_domains; > + u32 val; > + > + fw_domains = intel_uncore_forcewake_for_reg(uncore, reg, > + FW_REG_READ); > + fw_domains |= intel_uncore_forcewake_for_reg(uncore, > + GEN8_MCR_SELECTOR, > + FW_REG_READ | > FW_REG_WRITE); > + > + spin_lock_irq(&uncore->lock); > + intel_uncore_forcewake_get__locked(uncore, fw_domains); > + > + val = intel_uncore_read_with_mcr_steering_fw(uncore, reg, slice, > subslice); > + > + intel_uncore_forcewake_put__locked(uncore, fw_domains); > + spin_unlock_irq(&uncore->lock); > + > + return val; > +} > + > #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) > #include "selftests/mock_uncore.c" > #include "selftests/intel_uncore.c" > diff --git a/drivers/gpu/drm/i915/intel_uncore.h > b/drivers/gpu/drm/i915/intel_uncore.h > index 59f0da8f1fbb..a18bdb57af7b 100644 > --- a/drivers/gpu/drm/i915/intel_uncore.h > +++ b/drivers/gpu/drm/i915/intel_uncore.h > @@ -182,6 +182,12 @@ intel_uncore_has_fifo(const struct intel_uncore *uncore) > return uncore->flags & UNCORE_HAS_FIFO; > } > > +u32 intel_uncore_read_with_mcr_steering_fw(struct intel_uncore *uncore, > + i915_reg_t reg, > + int slice, int subslice); > +u32 intel_uncore_read_with_mcr_steering(struct intel_uncore *uncore, > + i915_reg_t reg, int slice, int > subslice); > + > void > intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug > *mmio_debug); > void intel_uncore_init_early(struct intel_uncore *uncore, > -- > 2.25.4 > > _______________________________________________ > Intel-gfx mailing list > [email protected] > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
