We should no longer increment level 0 by 1usec when we have 16Gb DIMMs.
Instead spec says to add 3usec (as opposed to 2) to each valid level
when punit replies 0 to level 0.
So set wm_lv_0_adjust_needed to false for DISPLAY_VER() >= 12 and set
the proper adjustement value when handling WaWmMemoryReadLatency.
Signed-off-by: Lucas De Marchi <lucas.demar...@intel.com>
---
drivers/gpu/drm/i915/intel_dram.c | 3 +--
drivers/gpu/drm/i915/intel_pm.c | 13 +++++++------
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dram.c
b/drivers/gpu/drm/i915/intel_dram.c
index 50fdea84ba70..879b0f007be3 100644
--- a/drivers/gpu/drm/i915/intel_dram.c
+++ b/drivers/gpu/drm/i915/intel_dram.c
@@ -484,8 +484,7 @@ static int gen11_get_dram_info(struct drm_i915_private
*i915)
static int gen12_get_dram_info(struct drm_i915_private *i915)
{
- /* Always needed for GEN12+ */
- i915->dram_info.wm_lv_0_adjust_needed = true;
+ i915->dram_info.wm_lv_0_adjust_needed = false;
return icl_pcode_read_mem_global_info(i915);
}
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ef8d9b2284b3..be2931d54b95 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2911,18 +2911,20 @@ static void intel_read_wm_latency(struct
drm_i915_private *dev_priv,
}
/*
- * WaWmMemoryReadLatency:skl+,glk
+ * WaWmMemoryReadLatency
*
* punit doesn't take into account the read latency so we need
- * to add 2us to the various latency levels we retrieve from the
- * punit when level 0 response data us 0us.
+ * to add proper adjustement to each valid level we retrieve
+ * from the punit when level 0 response data is 0us.
*/
if (wm[0] == 0) {
- wm[0] += 2;
+ u8 adjust = DISPLAY_VER(dev_priv) >= 12 ? 3 : 2;
+
+ wm[0] += adjust;
for (level = 1; level <= max_level; level++) {
if (wm[level] == 0)
break;
- wm[level] += 2;
+ wm[level] += adjust;
}
}
@@ -2934,7 +2936,6 @@ static void intel_read_wm_latency(struct drm_i915_private
*dev_priv,
*/
if (dev_priv->dram_info.wm_lv_0_adjust_needed)
wm[0] += 1;
-
} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
u64 sskpd = intel_uncore_read64(uncore, MCH_SSKPD);
--
2.31.1
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