Reviewed-by: Caz Yokoyama <caz.yokoy...@intel.com>
-caz
On Tue, 2021-07-13 at 20:15 -0700, Matt Roper wrote:
> DG2 supports compute DSS and has the same maximum number of DSS and
> EU
> as XeHP SDV.
>
> Signed-off-by: Matt Roper <matthew.d.ro...@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_sseu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c
> b/drivers/gpu/drm/i915/gt/intel_sseu.c
> index 5d3b8dff464c..eaff221db5b0 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu.c
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
> @@ -171,7 +171,7 @@ static void gen12_sseu_info_init(struct intel_gt
> *gt)
> * across the entire device. Then calculate out the DSS for
> each
> * workload type within that software slice.
> */
> - if (IS_XEHPSDV(gt->i915)) {
> + if (IS_DG2(gt->i915) || IS_XEHPSDV(gt->i915)) {
> intel_sseu_set_info(sseu, 1, 32, 16);
> sseu->has_compute_dss = 1;
> } else {
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