On Wed, Aug 18, 2021 at 09:10:48PM +0300, Jani Nikula wrote: > UHBR rates and 128b/132b channel encoding go hand in hand. > > Reviewed-by: Manasi Navare <[email protected]> > Signed-off-by: Jani Nikula <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_dp_link_training.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c > b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > index 031c753fca56..01f0adc585d0 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > @@ -495,7 +495,8 @@ intel_dp_prepare_link_train(struct intel_dp *intel_dp, > &rate_select, 1); > > link_config[0] = crtc_state->vrr.enable ? DP_MSA_TIMING_PAR_IGNORE_EN : > 0; > - link_config[1] = DP_SET_ANSI_8B10B; > + link_config[1] = crtc_state->port_clock > 1000000 ?
Should this be >= ? > + DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B; > drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2); > > intel_dp->DP |= DP_PORT_EN; > -- > 2.20.1 -- Ville Syrjälä Intel
