On Mon, Aug 30, 2021 at 09:52:38PM +0530, Ayaz A Siddiqui wrote: > In order to program unused and reserved mocs entries to L3_WB, > we need to create a separate mocs table for alderlake.
As noted on the previous patch, I don't think we need a separate table if we just make sure we initialize unused_entries_index differently for TGL/RKL vs other gen12 platforms (entry 2 vs entry 1). > > This patch will also covers wa_1608975824. > > Cc: Chris P Wilson <[email protected]> > Cc: Lucas De Marchi <[email protected]> > > Reviewed-by: Matt Roper <[email protected]> > Signed-off-by: Ayaz A Siddiqui <[email protected]> > --- > drivers/gpu/drm/i915/gt/intel_mocs.c | 41 +++++++++++++++++++++++++++- > 1 file changed, 40 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c > b/drivers/gpu/drm/i915/gt/intel_mocs.c > index a97cc08e5a395..577a78dfedf99 100644 > --- a/drivers/gpu/drm/i915/gt/intel_mocs.c > +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c > @@ -339,6 +339,39 @@ static const struct drm_i915_mocs_entry dg1_mocs_table[] > = { > MOCS_ENTRY(63, 0, L3_1_UC), > }; > > +static const struct drm_i915_mocs_entry adl_mocs_table[] = { > + /* wa_1608975824 */ > + MOCS_ENTRY(0, > + LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), Even if we want to keep the separate table for some reason, I believe this is the same as entry 2, right (which is defined inside GEN11_MOCS_ENTRIES)? So if we just omit it, it will be handled just like any other undefined entry. Matt > + > + GEN11_MOCS_ENTRIES, > + /* Implicitly enable L1 - HDC:L1 + L3 + LLC */ > + MOCS_ENTRY(48, > + LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + /* Implicitly enable L1 - HDC:L1 + L3 */ > + MOCS_ENTRY(49, > + LE_1_UC | LE_TC_1_LLC, > + L3_3_WB), > + /* Implicitly enable L1 - HDC:L1 + LLC */ > + MOCS_ENTRY(50, > + LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_1_UC), > + /* Implicitly enable L1 - HDC:L1 */ > + MOCS_ENTRY(51, > + LE_1_UC | LE_TC_1_LLC, > + L3_1_UC), > + /* HW Special Case (CCS) */ > + MOCS_ENTRY(60, > + LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_1_UC), > + /* HW Special Case (Displayable) */ > + MOCS_ENTRY(61, > + LE_1_UC | LE_TC_1_LLC, > + L3_3_WB), > +}; > + > enum { > HAS_GLOBAL_MOCS = BIT(0), > HAS_ENGINE_MOCS = BIT(1), > @@ -464,7 +497,13 @@ static unsigned int get_mocs_settings(const struct > drm_i915_private *i915, > > memset(table, 0, sizeof(struct drm_i915_mocs_table)); > > - if (IS_DG1(i915)) { > + if (IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) { > + table->size = ARRAY_SIZE(adl_mocs_table); > + table->table = adl_mocs_table; > + table->n_entries = GEN9_NUM_MOCS_ENTRIES; > + table->uc_index = 3; > + table->unused_entries_index = 2; > + } else if (IS_DG1(i915)) { > table->size = ARRAY_SIZE(dg1_mocs_table); > table->table = dg1_mocs_table; > table->n_entries = GEN9_NUM_MOCS_ENTRIES; > -- > 2.26.2 > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795
