MIPI DSI transcoder cannot be in video mode to support any of the
display C states.
Bspec: 49195 (For DC*co DSI transcoders cannot be in video mode)
Bspec: 49193 (Hardware does not support DC5 or DC6 with MIPI DSI enabled)
Bspec: 49188 (desc of DSI_DCSTATE_CTL talks about cmd mode PM control
v2: Align to the power domain ordering (Jani)
Add bspec references (Imre)
Signed-off-by: Vandita Kulkarni <vandita.kulka...@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index d88da0d0f05a..b989ddd3d023 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -3106,6 +3106,7 @@ intel_display_power_put_mask_in_set(struct
drm_i915_private *i915,
BIT_ULL(POWER_DOMAIN_MODESET) | \
BIT_ULL(POWER_DOMAIN_AUX_A) | \
BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define XELPD_AUX_IO_D_XELPD_POWER_DOMAINS
BIT_ULL(POWER_DOMAIN_AUX_D_XELPD)
--
2.32.0
