On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote: > From: Ville Syrjälä <[email protected]> > > Let's just stick to 32bit mmio accesses so we can get rid > of the bare "uncore" reg access in display code. The register > are defined as 32bit in the spec anyway. > > We could define a 64bit "de" variant I suppose, but doesn't > really make much sense just for this one case, and when we > start to use the DSB for this stuff we'd also need another > 64bit variant for that. Just easier to do 32bit always. > > While at it we can reorder stuff a bit so that we write the > registers in order of increasing offset (more or less).
Reviewed-by: José Roberto de Souza <[email protected]> > > Signed-off-by: Ville Syrjälä <[email protected]> > --- > drivers/gpu/drm/i915/display/skl_universal_plane.c | 11 +++++++---- > drivers/gpu/drm/i915/i915_reg.h | 12 ++++++------ > 2 files changed, 13 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c > b/drivers/gpu/drm/i915/display/skl_universal_plane.c > index 28890876bdeb..845b99844ec6 100644 > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c > @@ -1047,6 +1047,13 @@ skl_program_plane_noarm(struct intel_plane *plane, > intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id), > (src_h << 16) | src_w); > > + if (intel_fb_is_rc_ccs_cc_modifier(fb->modifier)) { > + intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 0), > + lower_32_bits(plane_state->ccval)); > + intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 1), > + upper_32_bits(plane_state->ccval)); > + } > + > if (icl_is_hdr_plane(dev_priv, plane_id)) > intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id), > plane_state->cus_ctl); > @@ -1054,10 +1061,6 @@ skl_program_plane_noarm(struct intel_plane *plane, > if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id)) > icl_program_input_csc(plane, crtc_state, plane_state); > > - if (intel_fb_is_rc_ccs_cc_modifier(fb->modifier)) > - intel_uncore_write64_fw(&dev_priv->uncore, > - PLANE_CC_VAL(pipe, plane_id), > plane_state->ccval); > - > skl_write_plane_wm(plane, crtc_state); > > intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, > color_plane); > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 3450818802c2..3c0471f20e53 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -7363,12 +7363,12 @@ enum { > #define _PLANE_NV12_BUF_CFG_1_A 0x70278 > #define _PLANE_NV12_BUF_CFG_2_A 0x70378 > > -#define _PLANE_CC_VAL_1_B 0x711b4 > -#define _PLANE_CC_VAL_2_B 0x712b4 > -#define _PLANE_CC_VAL_1(pipe) _PIPE(pipe, _PLANE_CC_VAL_1_A, > _PLANE_CC_VAL_1_B) > -#define _PLANE_CC_VAL_2(pipe) _PIPE(pipe, _PLANE_CC_VAL_2_A, > _PLANE_CC_VAL_2_B) > -#define PLANE_CC_VAL(pipe, plane) \ > - _MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), _PLANE_CC_VAL_2(pipe)) > +#define _PLANE_CC_VAL_1_B 0x711b4 > +#define _PLANE_CC_VAL_2_B 0x712b4 > +#define _PLANE_CC_VAL_1(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_1_A, > _PLANE_CC_VAL_1_B) + (dw) * 4) > +#define _PLANE_CC_VAL_2(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_2_A, > _PLANE_CC_VAL_2_B) + (dw) * 4) > +#define PLANE_CC_VAL(pipe, plane, dw) \ > + _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), > _PLANE_CC_VAL_2((pipe), (dw))) > > /* Input CSC Register Definitions */ > #define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0
