Currently 12 BPC PORT_OUTPUT_BPC bits are set in PIPE_MISC register for all Display > 12. DG2 is an exception. This patch tweaks the condition to read and write the above bits for DG2.
Signed-off-by: Ankit Nautiyal <[email protected]> --- drivers/gpu/drm/i915/display/intel_display.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index bf7ce684dd8e..1655cff7794f 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -3774,8 +3774,8 @@ static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state) val |= PIPEMISC_10_BPC; break; case 36: - /* Port output 12BPC defined for ADLP+ */ - if (DISPLAY_VER(dev_priv) > 12) + /* Port output 12BPC defined for ADLP+ except for DG2 */ + if (DISPLAY_VER(dev_priv) > 12 && !IS_DG2(dev_priv)) val |= PIPEMISC_12_BPC_ADLP; break; default: @@ -3835,7 +3835,7 @@ int bdw_get_pipemisc_bpp(struct intel_crtc *crtc) case PIPEMISC_10_BPC: return 30; /* - * PORT OUTPUT 12 BPC defined for ADLP+. + * PORT OUTPUT 12 BPC defined for ADLP+ (except DG2) * * TODO: * For previous platforms with DSI interface, bits 5:7 @@ -3845,7 +3845,7 @@ int bdw_get_pipemisc_bpp(struct intel_crtc *crtc) * MIPI DSI HW readout. */ case PIPEMISC_12_BPC_ADLP: - if (DISPLAY_VER(dev_priv) > 12) + if (DISPLAY_VER(dev_priv) > 12 && !IS_DG2(dev_priv)) return 36; fallthrough; default: -- 2.25.1
