From: Ville Syrjälä <[email protected]> Use chv_calc_dpll_params() to calculate the BXT DP DPLL VCO frequency.
We need to add the m1 divider into bxt_dp_clk_val[] for this to work. v2: Make the WARN_ON() sensible Signed-off-by: Ville Syrjälä <[email protected]> --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 23 +++++++++++-------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index 58e9d5960bc6..a5fc63401f49 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -2082,19 +2082,19 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, /* pre-calculated values for DP linkrates */ static const struct dpll bxt_dp_clk_val[] = { - { .dot = 162000, .p1 = 4, .p2 = 2, .n = 1, + { .dot = 162000, .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a /* .m2_int = 32, m2_frac = 1677722 */ }, - { .dot = 270000, .p1 = 4, .p2 = 1, .n = 1, + { .dot = 270000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 /* .m2_int = 27, m2_frac = 0 */ }, - { .dot = 540000, .p1 = 2, .p2 = 1, .n = 1, + { .dot = 540000, .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 /* .m2_int = 27, m2_frac = 0 */ }, - { .dot = 216000, .p1 = 3, .p2 = 2, .n = 1, + { .dot = 216000, .p1 = 3, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a /* .m2_int = 32, m2_frac = 1677722 */ }, - { .dot = 243000, .p1 = 4, .p2 = 1, .n = 1, + { .dot = 243000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6133333 /* .m2_int = 24, m2_frac = 1258291 */ }, - { .dot = 324000, .p1 = 4, .p2 = 1, .n = 1, + { .dot = 324000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x819999a /* .m2_int = 32, m2_frac = 1677722 */ }, - { .dot = 432000, .p1 = 3, .p2 = 1, .n = 1, + { .dot = 432000, .p1 = 3, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x819999a /* .m2_int = 32, m2_frac = 1677722 */ }, }; @@ -2125,18 +2125,21 @@ bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state, static void bxt_ddi_dp_pll_dividers(struct intel_crtc_state *crtc_state, struct dpll *clk_div) { - int clock = crtc_state->port_clock; + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); int i; *clk_div = bxt_dp_clk_val[0]; for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) { - if (bxt_dp_clk_val[i].dot == clock) { + if (crtc_state->port_clock == bxt_dp_clk_val[i].dot) { *clk_div = bxt_dp_clk_val[i]; break; } } - clk_div->vco = clock * 10 / 2 * clk_div->p1 * clk_div->p2; + chv_calc_dpll_params(i915->dpll.ref_clks.nssc, clk_div); + + drm_WARN_ON(&i915->drm, clk_div->vco == 0 || + clk_div->dot != crtc_state->port_clock); } static bool bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state, -- 2.34.1
