On Thu, 10 Mar 2022, Ville Syrjala <[email protected]> wrote: > From: Ville Syrjälä <[email protected]> > > VBT hsa a field for the MSA timing delay, which supposedly > should be used with DRRS. Extract the data from the VBT. > > Signed-off-by: Ville Syrjälä <[email protected]>
Reviewed-by: Jani Nikula <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_bios.c | 3 +++ > drivers/gpu/drm/i915/i915_drv.h | 5 +++-- > 2 files changed, 6 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c > b/drivers/gpu/drm/i915/display/intel_bios.c > index a559a1914588..93dc32fb3e40 100644 > --- a/drivers/gpu/drm/i915/display/intel_bios.c > +++ b/drivers/gpu/drm/i915/display/intel_bios.c > @@ -888,6 +888,9 @@ parse_edp(struct drm_i915_private *i915, const struct > bdb_header *bdb) > i915->vbt.edp.low_vswing = vswing == 0; > } > } > + > + i915->vbt.edp.drrs_msa_timing_delay = > + (edp->sdrrs_msa_timing_delay >> (panel_type * 2)) & 3; > } > > static void > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 943267393ecb..020c5f7602a2 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -356,10 +356,11 @@ struct intel_vbt_data { > int lanes; > int preemphasis; > int vswing; > - bool low_vswing; > - bool initialized; > int bpp; > struct edp_power_seq pps; > + u8 drrs_msa_timing_delay; > + bool low_vswing; > + bool initialized; > bool hobl; > } edp; -- Jani Nikula, Intel Open Source Graphics Center
