On Fri, Mar 25, 2022 at 07:22:49AM -0700, José Roberto de Souza wrote: > New DG2 workaround added to specification. > > BSpec: 54077 > BSpec: 66622 > BSpec: 54833 > Cc: Matt Roper <[email protected]> > Signed-off-by: José Roberto de Souza <[email protected]>
Reviewed-by: Matt Roper <[email protected]> > --- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + > drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++ > 2 files changed, 6 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > index 62e0f075b1de7..17432b075d970 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > @@ -1088,6 +1088,7 @@ > #define EU_PERF_CNTL3 _MMIO(0xe758) > > #define LSC_CHICKEN_BIT_0 _MMIO(0xe7c8) > +#define DISABLE_D8_D16_COASLESCE REG_BIT(30) > #define FORCE_1_SUB_MESSAGE_PER_FRAGMENT REG_BIT(15) > #define LSC_CHICKEN_BIT_0_UDW _MMIO(0xe7c8 + 4) > #define DIS_CHAIN_2XSIMD8 REG_BIT(55 - 32) > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c > b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index dc0ffff6f655a..29c8cd0a81b6f 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -2624,6 +2624,11 @@ general_render_compute_wa_init(struct intel_engine_cs > *engine, struct i915_wa_li > wa_write_or(wal, GEN12_GAMCNTRL_CTRL, > INVALIDATION_BROADCAST_MODE_DIS | > GLOBAL_INVALIDATION_MODE); > } > + > + if (IS_DG2(i915)) { > + /* Wa_22014226127:dg2 */ > + wa_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE); > + } > } > > static void > -- > 2.35.1 > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795
