[Intel-gfx] [PATCH] drm/i915/display: Implement Wa_14015648006

[Mika Kahola]

Add 4th pipe to extend TGL Wa_16013835468 to support DG2
platform.

BSpec: 54077

Cc: Jouni Högander <jouni.hogan...@intel.com>
Cc: José Roberto de Souza <jose.so...@intel.com>
Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 7 +++++--
 drivers/gpu/drm/i915/i915_reg.h          | 1 +
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
b/drivers/gpu/drm/i915/display/intel_psr.c
index 06db407e2749..d3b47c612305 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1080,6 +1080,8 @@ static u32 wa_16013835468_bit_get(struct intel_dp 
*intel_dp)
                return LATENCY_REPORTING_REMOVED_PIPE_B;
        case PIPE_C:
                return LATENCY_REPORTING_REMOVED_PIPE_C;
+       case PIPE_D:
+               return LATENCY_REPORTING_REMOVED_PIPE_D;
        default:
                MISSING_CASE(intel_dp->psr.pipe);
                return 0;
@@ -1159,8 +1161,9 @@ static void intel_psr_enable_source(struct intel_dp 
*intel_dp,
                                     CLKGATE_DIS_MISC_DMASC_GATING_DIS);
 
                /* Wa_16013835468:tgl[b0+], dg1 */
-               if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER) ||
-                   IS_DG1(dev_priv)) {
+               /* Wa_14015648006: dg2 */
+               if (DISPLAY_VER(dev_priv) >= 12 &&
+                   !IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
                        u16 vtotal, vblank;
 
                        vtotal = crtc_state->uapi.adjusted_mode.crtc_vtotal -
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9ccb67eec1bd..b01402647300 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5921,6 +5921,7 @@
 #define  RESET_PCH_HANDSHAKE_ENABLE    (1 << 4)
 
 #define GEN8_CHICKEN_DCPR_1                    _MMIO(0x46430)
+#define   LATENCY_REPORTING_REMOVED_PIPE_D     REG_BIT(31)
 #define   SKL_SELECT_ALTERNATE_DC_EXIT         REG_BIT(30)
 #define   LATENCY_REPORTING_REMOVED_PIPE_C     REG_BIT(25)
 #define   LATENCY_REPORTING_REMOVED_PIPE_B     REG_BIT(24)
-- 
2.27.0