On Mon, May 09, 2022 at 03:01:30PM +0530, Ankit Nautiyal wrote: > As per Sec 7.8.1 of HDMI2.1 spec, sources that support modes: > 4K100, 4K120, 8K50, 8K60 must support these modes in at least one of > the below formats: > i) uncompressed FRL, 420 format and min of 10 bpc, or > ii) compressed FRL, 444 format and min of 10 bpc. > > Since FRL and DSC are not supported natively with HDMI, the above > modes must be pruned as per the spec, and is a requirement for the > HDMI2.1 compliance test. > > This patch adds a condition to check for the modes with clock > requirement more than 2376 MHz (1188 MHz with 420 format), > and prune them if none of the above two formats are supported.
Wy are we trying to pass HDMI-2.1 tests on a device that doesn't even support HDMI-2.1? > > Signed-off-by: Ankit Nautiyal <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_hdmi.c | 48 +++++++++++++++++++++++ > 1 file changed, 48 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c > b/drivers/gpu/drm/i915/display/intel_hdmi.c > index 1ae09431f53a..2ee1262f6427 100644 > --- a/drivers/gpu/drm/i915/display/intel_hdmi.c > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c > @@ -1940,6 +1940,44 @@ static bool intel_hdmi_sink_bpc_possible(struct > drm_connector *connector, > } > } > > +/* > + * HDMI2.1 Sec7.8.1 > + * Support requirement for 4K100, 4K120, 8K50, and 8K60. > + * > + * The modes with timings same as above modes are supported only with min of > 10 bpc > + * along with: > + * > + * i) 444 format only with FRL mode support with DSC > + * ii) 420 format only with FRL mode without DSC. > + */ > +static bool > +intel_hdmi21_bpc_possible(struct drm_connector *connector, > + int clock, int bpc, bool ycbcr420_output, > + bool frl, bool dsc) > +{ > + const struct drm_display_info *info = &connector->display_info; > + const struct drm_hdmi_info *hdmi = &info->hdmi; > + > + int pixel_clock = ycbcr420_output ? clock * 2 : clock; > + > + if (pixel_clock < 2376000) > + return true; > + > + if (!frl) > + return false; > + > + if (dsc && bpc > hdmi->dsc_cap.bpc_supported) > + return false; > + > + if (!ycbcr420_output && !dsc) > + return false; > + > + if (bpc < 10) > + return false; > + > + return true; > +} > + > static enum drm_mode_status > intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock, > bool has_hdmi_sink, bool ycbcr420_output) > @@ -1948,6 +1986,13 @@ intel_hdmi_mode_clock_valid(struct drm_connector > *connector, int clock, > struct intel_hdmi *hdmi = > intel_attached_hdmi(to_intel_connector(connector)); > enum drm_mode_status status = MODE_OK; > int bpc; > + bool frl, dsc; > + > + /* > + * FRL and DSC not supported for HDMI from source as of now. > + */ > + frl = false; > + dsc = false; > > /* > * Try all color depths since valid port clock range > @@ -1963,6 +2008,9 @@ intel_hdmi_mode_clock_valid(struct drm_connector > *connector, int clock, > if (!intel_hdmi_sink_bpc_possible(connector, bpc, > has_hdmi_sink, ycbcr420_output)) > continue; > > + if (!intel_hdmi21_bpc_possible(connector, clock, bpc, > ycbcr420_output, frl, dsc)) > + continue; > + > status = hdmi_port_clock_valid(hdmi, tmds_clock, true, > has_hdmi_sink); > if (status == MODE_OK) > return MODE_OK; > -- > 2.25.1 -- Ville Syrjälä Intel
