Currently we reuse hsw_crtc_enable for SKL+ platforms.
But this has added a lot of platform checks for SKL+ platforms.
So its time to move the code to a separate crtc_enable hook
for SKL+ platforms.
No functional changes here.
v2: Cleanup hsw_crtc_enable (Jani N)
Suggested-by: Jani Nikula <jani.nik...@intel.com>
Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
Cc: Jani Nikula <jani.nik...@intel.com>
Signed-off-by: Manasi Navare <manasi.d.nav...@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 64 ++++++++++++++++----
1 file changed, 52 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 806d50b302ab..70cde34aca10 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1895,13 +1895,13 @@ static void hsw_configure_cpu_transcoder(const struct
intel_crtc_state *crtc_sta
hsw_set_transconf(crtc_state);
}
-static void hsw_crtc_enable(struct intel_atomic_state *state,
+static void skl_crtc_enable(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
const struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
+ enum pipe pipe = crtc->pipe;
enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
bool psl_clkgate_wa;
@@ -1925,8 +1925,7 @@ static void hsw_crtc_enable(struct intel_atomic_state
*state,
intel_uncompressed_joiner_enable(new_crtc_state);
intel_set_pipe_src_size(new_crtc_state);
- if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
- bdw_set_pipemisc(new_crtc_state);
+ bdw_set_pipemisc(new_crtc_state);
if (!intel_crtc_is_bigjoiner_slave(new_crtc_state) &&
!transcoder_is_dsi(cpu_transcoder))
@@ -1940,10 +1939,7 @@ static void hsw_crtc_enable(struct intel_atomic_state
*state,
if (psl_clkgate_wa)
glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
- if (DISPLAY_VER(dev_priv) >= 9)
- skl_pfit_enable(new_crtc_state);
- else
- ilk_pfit_enable(new_crtc_state);
+ skl_pfit_enable(new_crtc_state);
/*
* On ILK+ LUT must be loaded before the pipe is running but with
@@ -1952,9 +1948,6 @@ static void hsw_crtc_enable(struct intel_atomic_state
*state,
intel_color_load_luts(new_crtc_state);
intel_color_commit_noarm(new_crtc_state);
intel_color_commit_arm(new_crtc_state);
- /* update DSPCNTR to configure gamma/csc for pipe bottom color */
- if (DISPLAY_VER(dev_priv) < 9)
- intel_disable_primary_plane(new_crtc_state);
hsw_set_linetime_wm(new_crtc_state);
@@ -1972,6 +1965,53 @@ static void hsw_crtc_enable(struct intel_atomic_state
*state,
intel_crtc_wait_for_next_vblank(crtc);
glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
}
+}
+
+static void hsw_crtc_enable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+ const struct intel_crtc_state *new_crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe hsw_workaround_pipe;
+ enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
+
+ if (drm_WARN_ON(&dev_priv->drm, crtc->active))
+ return;
+
+ intel_encoders_pre_pll_enable(state, crtc);
+
+ if (new_crtc_state->shared_dpll)
+ intel_enable_shared_dpll(new_crtc_state);
+
+ intel_encoders_pre_enable(state, crtc);
+
+ intel_set_pipe_src_size(new_crtc_state);
+ if (IS_BROADWELL(dev_priv))
+ bdw_set_pipemisc(new_crtc_state);
+
+ if (!transcoder_is_dsi(cpu_transcoder))
+ hsw_configure_cpu_transcoder(new_crtc_state);
+
+ crtc->active = true;
+
+ ilk_pfit_enable(new_crtc_state);
+
+ /*
+ * On ILK+ LUT must be loaded before the pipe is running but with
+ * clocks enabled
+ */
+ intel_color_load_luts(new_crtc_state);
+ intel_color_commit_noarm(new_crtc_state);
+ intel_color_commit_arm(new_crtc_state);
+ /* update DSPCNTR to configure gamma/csc for pipe bottom color */
+ intel_disable_primary_plane(new_crtc_state);
+
+ hsw_set_linetime_wm(new_crtc_state);
+
+ intel_initial_watermarks(state, crtc);
+
+ intel_encoders_enable(state, crtc);
/* If we change the relative order between pipe/planes enabling, we need
* to change the workaround. */
@@ -9231,7 +9271,7 @@ static const struct drm_mode_config_funcs
intel_mode_funcs = {
static const struct drm_i915_display_funcs skl_display_funcs = {
.get_pipe_config = hsw_get_pipe_config,
- .crtc_enable = hsw_crtc_enable,
+ .crtc_enable = skl_crtc_enable,
.crtc_disable = hsw_crtc_disable,
.commit_modeset_enables = skl_commit_modeset_enables,
.get_initial_plane_config = skl_get_initial_plane_config,
--
2.35.1
