On Fri, 17 Jun 2022, Ville Syrjala <[email protected]> wrote: > From: Ville Syrjälä <[email protected]> > > Shuffle some PLL functions around a bit to avoid ugle > forward declarations later on. No functional changes. > > Signed-off-by: Ville Syrjälä <[email protected]>
Reviewed-by: Jani Nikula <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 176 +++++++++--------- > 1 file changed, 88 insertions(+), 88 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > index ddae7e42ac46..bfccc96f16fe 100644 > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > @@ -905,37 +905,6 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */, > *r2_out = best.r2; > } > > -static int > -hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state, > - struct intel_crtc *crtc) > -{ > - struct intel_crtc_state *crtc_state = > - intel_atomic_get_new_crtc_state(state, crtc); > - unsigned int p, n2, r2; > - > - hsw_ddi_calculate_wrpll(crtc_state->port_clock * 1000, &r2, &n2, &p); > - > - crtc_state->dpll_hw_state.wrpll = > - WRPLL_PLL_ENABLE | WRPLL_REF_LCPLL | > - WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) | > - WRPLL_DIVIDER_POST(p); > - > - return 0; > -} > - > -static struct intel_shared_dpll * > -hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state, > - struct intel_crtc *crtc) > -{ > - struct intel_crtc_state *crtc_state = > - intel_atomic_get_new_crtc_state(state, crtc); > - > - return intel_find_shared_dpll(state, crtc, > - &crtc_state->dpll_hw_state, > - BIT(DPLL_ID_WRPLL2) | > - BIT(DPLL_ID_WRPLL1)); > -} > - > static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv, > const struct intel_shared_dpll *pll, > const struct intel_dpll_hw_state *pll_state) > @@ -976,6 +945,37 @@ static int hsw_ddi_wrpll_get_freq(struct > drm_i915_private *dev_priv, > return (refclk * n / 10) / (p * r) * 2; > } > > +static int > +hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state, > + struct intel_crtc *crtc) > +{ > + struct intel_crtc_state *crtc_state = > + intel_atomic_get_new_crtc_state(state, crtc); > + unsigned int p, n2, r2; > + > + hsw_ddi_calculate_wrpll(crtc_state->port_clock * 1000, &r2, &n2, &p); > + > + crtc_state->dpll_hw_state.wrpll = > + WRPLL_PLL_ENABLE | WRPLL_REF_LCPLL | > + WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) | > + WRPLL_DIVIDER_POST(p); > + > + return 0; > +} > + > +static struct intel_shared_dpll * > +hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state, > + struct intel_crtc *crtc) > +{ > + struct intel_crtc_state *crtc_state = > + intel_atomic_get_new_crtc_state(state, crtc); > + > + return intel_find_shared_dpll(state, crtc, > + &crtc_state->dpll_hw_state, > + BIT(DPLL_ID_WRPLL2) | > + BIT(DPLL_ID_WRPLL1)); > +} > + > static int > hsw_ddi_lcpll_compute_dpll(struct intel_crtc_state *crtc_state) > { > @@ -1618,43 +1618,6 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */, > return 0; > } > > -static int skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state) > -{ > - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); > - struct skl_wrpll_params wrpll_params = {}; > - u32 ctrl1, cfgcr1, cfgcr2; > - int ret; > - > - /* > - * See comment in intel_dpll_hw_state to understand why we always use 0 > - * as the DPLL id in this function. > - */ > - ctrl1 = DPLL_CTRL1_OVERRIDE(0); > - > - ctrl1 |= DPLL_CTRL1_HDMI_MODE(0); > - > - ret = skl_ddi_calculate_wrpll(crtc_state->port_clock * 1000, > - i915->dpll.ref_clks.nssc, &wrpll_params); > - if (ret) > - return ret; > - > - cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE | > - DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) | > - wrpll_params.dco_integer; > - > - cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) | > - DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) | > - DPLL_CFGCR2_KDIV(wrpll_params.kdiv) | > - DPLL_CFGCR2_PDIV(wrpll_params.pdiv) | > - wrpll_params.central_freq; > - > - crtc_state->dpll_hw_state.ctrl1 = ctrl1; > - crtc_state->dpll_hw_state.cfgcr1 = cfgcr1; > - crtc_state->dpll_hw_state.cfgcr2 = cfgcr2; > - > - return 0; > -} > - > static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915, > const struct intel_shared_dpll *pll, > const struct intel_dpll_hw_state *pll_state) > @@ -1726,6 +1689,43 @@ static int skl_ddi_wrpll_get_freq(struct > drm_i915_private *i915, > return dco_freq / (p0 * p1 * p2 * 5); > } > > +static int skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state) > +{ > + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); > + struct skl_wrpll_params wrpll_params = {}; > + u32 ctrl1, cfgcr1, cfgcr2; > + int ret; > + > + /* > + * See comment in intel_dpll_hw_state to understand why we always use 0 > + * as the DPLL id in this function. > + */ > + ctrl1 = DPLL_CTRL1_OVERRIDE(0); > + > + ctrl1 |= DPLL_CTRL1_HDMI_MODE(0); > + > + ret = skl_ddi_calculate_wrpll(crtc_state->port_clock * 1000, > + i915->dpll.ref_clks.nssc, &wrpll_params); > + if (ret) > + return ret; > + > + cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE | > + DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) | > + wrpll_params.dco_integer; > + > + cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) | > + DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) | > + DPLL_CFGCR2_KDIV(wrpll_params.kdiv) | > + DPLL_CFGCR2_PDIV(wrpll_params.pdiv) | > + wrpll_params.central_freq; > + > + crtc_state->dpll_hw_state.ctrl1 = ctrl1; > + crtc_state->dpll_hw_state.cfgcr1 = cfgcr1; > + crtc_state->dpll_hw_state.cfgcr2 = cfgcr2; > + > + return 0; > +} > + > static int > skl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state) > { > @@ -2245,26 +2245,6 @@ static int bxt_ddi_set_dpll_hw_state(struct > intel_crtc_state *crtc_state, > return 0; > } > > -static int > -bxt_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state) > -{ > - struct dpll clk_div = {}; > - > - bxt_ddi_dp_pll_dividers(crtc_state, &clk_div); > - > - return bxt_ddi_set_dpll_hw_state(crtc_state, &clk_div); > -} > - > -static int > -bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state) > -{ > - struct dpll clk_div = {}; > - > - bxt_ddi_hdmi_pll_dividers(crtc_state, &clk_div); > - > - return bxt_ddi_set_dpll_hw_state(crtc_state, &clk_div); > -} > - > static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915, > const struct intel_shared_dpll *pll, > const struct intel_dpll_hw_state *pll_state) > @@ -2282,6 +2262,26 @@ static int bxt_ddi_pll_get_freq(struct > drm_i915_private *i915, > return chv_calc_dpll_params(i915->dpll.ref_clks.nssc, &clock); > } > > +static int > +bxt_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state) > +{ > + struct dpll clk_div = {}; > + > + bxt_ddi_dp_pll_dividers(crtc_state, &clk_div); > + > + return bxt_ddi_set_dpll_hw_state(crtc_state, &clk_div); > +} > + > +static int > +bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state) > +{ > + struct dpll clk_div = {}; > + > + bxt_ddi_hdmi_pll_dividers(crtc_state, &clk_div); > + > + return bxt_ddi_set_dpll_hw_state(crtc_state, &clk_div); > +} > + > static int bxt_compute_dpll(struct intel_atomic_state *state, > struct intel_crtc *crtc, > struct intel_encoder *encoder) -- Jani Nikula, Intel Open Source Graphics Center
