On Wed, Jun 22, 2022 at 09:38:36PM +0300, Lionel Landwerlin wrote:
This is the recommended value for optimal performance.
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 07ef111947b8c..a50b5790e434e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1112,6 +1112,9 @@
#define GEN12_PUSH_CONST_DEREF_HOLD_DIS REG_BIT(8)
#define RT_CTRL _MMIO(0xe530)
+#define NUMBER_OF_STACKIDS_512 (2 << 5)
+#define NUMBER_OF_STACKIDS_1024 (1 << 5)
+#define NUMBER_OF_STACKIDS_2048 (0 << 5)
Should be using REG_BIT / REG_FIELD_PREP
#define DIS_NULL_QUERY REG_BIT(10)
#define EU_PERF_CNTL1 _MMIO(0xe558)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 3213c593a55f4..a8a389d36986c 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2106,6 +2106,9 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct
i915_wa_list *wal)
* performance guide section.
*/
wa_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
+
+ /* Wa_18019455067:dg2 / BSpec 68331/54402 */
+ wa_write_or(wal, RT_CTRL, NUMBER_OF_STACKIDS_512);
this is not a workaround, it's a tuning value. See functions with
"tuning" in the name. Do not keep bspec reference in comment. If at all,
this should be in the commit message.
This is also not setting the correct value if it was previously
programmed with NUMBER_OF_STACKIDS_1024 since it will just OR the bits.
Use wa_write_clr_set().
Lucas De Marchi
