> -----Original Message----- > From: Lee, Shawn C <shawn.c....@intel.com> > Sent: Wednesday, July 13, 2022 2:57 PM > To: intel-gfx@lists.freedesktop.org > Cc: Lee, Shawn C <shawn.c....@intel.com>; Jani Nikula > <jani.nik...@linux.intel.com>; Ville Syrjälä <ville.syrj...@linux.intel.com>; > Shankar, > Uma <uma.shan...@intel.com>; Lisovskiy, Stanislav > <stanislav.lisovs...@intel.com>; Tseng, William <william.ts...@intel.com> > Subject: [PATCH] drm/i915: clear plane color ctl setting when turn full plane > off
We can append "display" to drm/i915 > Customer report abnormal display output while switch eDP off sometimes. > In current display disable flow, plane will be off at first. Then turn eDP > off and disable > HW pipe line. We found the abnormal pixel comes after turn plane off. Clear > plane > color ctl register when driver disable plane can solve this symptom. Change Looks Good to me. Reviewed-by: Uma Shankar <uma.shan...@intel.com> > Cc: Jani Nikula <jani.nik...@linux.intel.com> > Cc: Ville Syrjälä <ville.syrj...@linux.intel.com> > Cc: Shankar Uma <uma.shan...@intel.com> > Cc: Stanislav Lisovskiy <stanislav.lisovs...@intel.com> > Cc: William Tseng <william.ts...@intel.com> > Signed-off-by: Lee Shawn C <shawn.c....@intel.com> > --- > drivers/gpu/drm/i915/display/skl_universal_plane.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c > b/drivers/gpu/drm/i915/display/skl_universal_plane.c > index caa03324a733..90977cfb7ebb 100644 > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c > @@ -620,6 +620,8 @@ skl_plane_disable_arm(struct intel_plane *plane, > > intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0); > intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0); > + if (DISPLAY_VER(dev_priv) >= 10) > + intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id), 0); > } > > static void > @@ -638,6 +640,7 @@ icl_plane_disable_arm(struct intel_plane *plane, > intel_psr2_disable_plane_sel_fetch(plane, crtc_state); > intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0); > intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0); > + intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id), 0); > } > > static bool > -- > 2.17.1