Hi Chris, We are using single write fifo for the multiple power wells. Since Valleyview as only supports only one write fifo.
Thanks Deepak -----Original Message----- From: Chris Wilson [mailto:ch...@chris-wilson.co.uk] Sent: Monday, November 25, 2013 8:18 PM To: S, Deepak Cc: intel-gfx@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH 2/3] drm/i915/vlv: Valleyview support for forcewake Individual power wells. On Sat, Nov 23, 2013 at 02:55:43PM +0530, deepa...@intel.com wrote: > From: Deepak S <deepa...@intel.com> > > Split vlv force wake routines to help individually control > Media/Render well based on the register access. Do you mind clarifying if there if a single write fifo for the multiple power wells? Just something that worried me reading through the code. Otherwise, lgtm. -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
