DG1 and DG2 has lmem, and cpu can access the lmem objects
via mmap and i915 internal i915_gem_object_pin_map() for
i915 own usages. Both of these methods has pre-requisite
requirement to keep GFX PCI endpoint in D0 for a supported
iomem transaction over PCI link. (Refer PCIe specs pecs 5.3.1.4.1)
TODO:
A solution towards releasing mmap mappings in runtime suspend is
already work in progress.
With respect to i915_gem_object_pin_map(), every caller
has to grab a wakeref if gem object lies in lmem.
Till we fix all issues related to runtime PM, we need
to keep runtime PM disable on both DG1 and DG2.
Cc: Matthew Auld <matthew.a...@intel.com>
Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gu...@intel.com>
---
drivers/gpu/drm/i915/i915_pci.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 77e7df21f539..28f38f1cc5cc 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -931,6 +931,7 @@ static const struct intel_device_info dg1_info = {
BIT(VCS0) | BIT(VCS2),
/* Wa_16011227922 */
.__runtime.ppgtt_size = 47,
+ .has_runtime_pm = 0,
};
static const struct intel_device_info adl_s_info = {
@@ -1076,6 +1077,7 @@ static const struct intel_device_info dg2_info = {
XE_LPD_FEATURES,
.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
+ .has_runtime_pm = 0,
.require_force_probe = 1,
};
--
2.26.2
