On Thu, Oct 27, 2022 at 03:15:51PM -0700, Daniele Ceraolo Spurio wrote:
> We need to tell the GuC that the GSC CS is there. The GuC interface
> swaps COMPUTE and OTHER class, so we also need to handle that.
When I first read the second sentence here, I thought you were saying
that the GuC interface had changed and redefined its own enums, but
that's not the case. I think you just meant that the FOO_CLASS and
GUC_FOO_CLASS enums are nearly the same except that they order COMPUTE
and OTHER classes differently. Honestly I think that's already pretty
clear from the existing values and mapping tables, even before this
patch, so I'd just leave this sentence off to avoid confusion.
Otherwise,
Reviewed-by: Matt Roper <matthew.d.ro...@intel.com>
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
> Cc: Matt Roper <matthew.d.ro...@intel.com>
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 11 +++++------
> drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 7 +++++--
> 2 files changed, 10 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> index 34ef4f36e660..63e3d98788bd 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> @@ -478,6 +478,11 @@ static void fill_engine_enable_masks(struct intel_gt *gt,
> info_map_write(info_map, engine_enabled_masks[GUC_BLITTER_CLASS],
> BCS_MASK(gt));
> info_map_write(info_map, engine_enabled_masks[GUC_VIDEO_CLASS],
> VDBOX_MASK(gt));
> info_map_write(info_map, engine_enabled_masks[GUC_VIDEOENHANCE_CLASS],
> VEBOX_MASK(gt));
> +
> + /* The GSC engine is an instance (6) of OTHER_CLASS */
> + if (gt->engine[GSC0])
> + info_map_write(info_map,
> engine_enabled_masks[GUC_GSC_OTHER_CLASS],
> + BIT(gt->engine[GSC0]->instance));
> }
>
> #define LR_HW_CONTEXT_SIZE (80 * sizeof(u32))
> @@ -519,9 +524,6 @@ static int guc_prep_golden_context(struct intel_guc *guc)
> }
>
> for (engine_class = 0; engine_class <= MAX_ENGINE_CLASS;
> ++engine_class) {
> - if (engine_class == OTHER_CLASS)
> - continue;
> -
> guc_class = engine_class_to_guc_class(engine_class);
>
> if (!info_map_read(&info_map, engine_enabled_masks[guc_class]))
> @@ -599,9 +601,6 @@ static void guc_init_golden_context(struct intel_guc *guc)
> addr_ggtt = intel_guc_ggtt_offset(guc, guc->ads_vma) + offset;
>
> for (engine_class = 0; engine_class <= MAX_ENGINE_CLASS;
> ++engine_class) {
> - if (engine_class == OTHER_CLASS)
> - continue;
> -
> guc_class = engine_class_to_guc_class(engine_class);
> if (!ads_blob_read(guc,
> system_info.engine_enabled_masks[guc_class]))
> continue;
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> index 968ebd79dce7..4ae5fc2f6002 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> @@ -47,7 +47,8 @@
> #define GUC_VIDEOENHANCE_CLASS 2
> #define GUC_BLITTER_CLASS 3
> #define GUC_COMPUTE_CLASS 4
> -#define GUC_LAST_ENGINE_CLASS GUC_COMPUTE_CLASS
> +#define GUC_GSC_OTHER_CLASS 5
> +#define GUC_LAST_ENGINE_CLASS GUC_GSC_OTHER_CLASS
> #define GUC_MAX_ENGINE_CLASSES 16
> #define GUC_MAX_INSTANCES_PER_CLASS 32
>
> @@ -169,6 +170,7 @@ static u8 engine_class_guc_class_map[] = {
> [COPY_ENGINE_CLASS] = GUC_BLITTER_CLASS,
> [VIDEO_DECODE_CLASS] = GUC_VIDEO_CLASS,
> [VIDEO_ENHANCEMENT_CLASS] = GUC_VIDEOENHANCE_CLASS,
> + [OTHER_CLASS] = GUC_GSC_OTHER_CLASS,
> [COMPUTE_CLASS] = GUC_COMPUTE_CLASS,
> };
>
> @@ -178,12 +180,13 @@ static u8 guc_class_engine_class_map[] = {
> [GUC_VIDEO_CLASS] = VIDEO_DECODE_CLASS,
> [GUC_VIDEOENHANCE_CLASS] = VIDEO_ENHANCEMENT_CLASS,
> [GUC_COMPUTE_CLASS] = COMPUTE_CLASS,
> + [GUC_GSC_OTHER_CLASS] = OTHER_CLASS,
> };
>
> static inline u8 engine_class_to_guc_class(u8 class)
> {
> BUILD_BUG_ON(ARRAY_SIZE(engine_class_guc_class_map) != MAX_ENGINE_CLASS
> + 1);
> - GEM_BUG_ON(class > MAX_ENGINE_CLASS || class == OTHER_CLASS);
> + GEM_BUG_ON(class > MAX_ENGINE_CLASS);
>
> return engine_class_guc_class_map[class];
> }
> --
> 2.37.3
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
