On Tue, Nov 22, 2022 at 02:31:55PM +0200, Jani Nikula wrote: > On Tue, 22 Nov 2022, Ville Syrjala <[email protected]> wrote: > > From: Ville Syrjälä <[email protected]> > > > > Poke a few more bits into the ch7xxx to make > > it output a picture after being reset during S3. > > > > In particular we need to set the input buffer select (IBS), > > and enable VGA vsync output on the BCO pin. Selecting > > VGA hsync on the c/h sync pin doesn't actually seem necessary > > on my ADD card at least, but the BIOS selects it so why not. > > > > Signed-off-by: Ville Syrjälä <[email protected]> > > First things first. > > I'll r-b anything that I've actually reviewed in the series, although > the subject matter being what it is, I may not have reviewed it as > thoroughly as I would other code that I review. > > If r-b would require me to look stuff up in the specs, I really couldn't > be bothered, so I'll just a-b that stuff if it looks reasonable. I don't > think anyone else is going to show up for review either, and if you end > up breaking something, I think you're the only one to show up to fix it > anyway. > > Fair enough?
Yeah, I think acks are good enough for these in general. > > With that, this patch is > > Acked-by: Jani Nikula <[email protected]> Thanks. Series pushed now. > > > --- > > drivers/gpu/drm/i915/display/dvo_ch7xxx.c | 22 ++++++++++++++++++++-- > > 1 file changed, 20 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/dvo_ch7xxx.c > > b/drivers/gpu/drm/i915/display/dvo_ch7xxx.c > > index 54f58ba44b9f..6d948520e9a6 100644 > > --- a/drivers/gpu/drm/i915/display/dvo_ch7xxx.c > > +++ b/drivers/gpu/drm/i915/display/dvo_ch7xxx.c > > @@ -50,15 +50,26 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. > > #define CH7xxx_INPUT_CLOCK 0x1d > > #define CH7xxx_GPIO 0x1e > > #define CH7xxx_GPIO_HPIR (1<<3) > > + > > #define CH7xxx_IDF 0x1f > > - > > +#define CH7xxx_IDF_IBS (1<<7) > > +#define CH7xxx_IDF_DES (1<<6) > > #define CH7xxx_IDF_HSP (1<<3) > > #define CH7xxx_IDF_VSP (1<<4) > > > > #define CH7xxx_CONNECTION_DETECT 0x20 > > #define CH7xxx_CDET_DVI (1<<5) > > > > -#define CH7301_DAC_CNTL 0x21 > > +#define CH7xxx_DAC_CNTL 0x21 > > +#define CH7xxx_SYNCO_MASK (3 << 3) > > +#define CH7xxx_SYNCO_VGA_HSYNC (1 << 3) > > + > > +#define CH7xxx_CLOCK_OUTPUT 0x22 > > +#define CH7xxx_BCOEN (1 << 4) > > +#define CH7xxx_BCOP (1 << 3) > > +#define CH7xxx_BCO_MASK (7 << 0) > > +#define CH7xxx_BCO_VGA_VSYNC (6 << 0) > > + > > #define CH7301_HOTPLUG 0x23 > > #define CH7xxx_TCTL 0x31 > > #define CH7xxx_TVCO 0x32 > > @@ -301,6 +312,8 @@ static void ch7xxx_mode_set(struct intel_dvo_device > > *dvo, > > > > ch7xxx_readb(dvo, CH7xxx_IDF, &idf); > > > > + idf |= CH7xxx_IDF_IBS; > > + > > idf &= ~(CH7xxx_IDF_HSP | CH7xxx_IDF_VSP); > > if (mode->flags & DRM_MODE_FLAG_PHSYNC) > > idf |= CH7xxx_IDF_HSP; > > @@ -309,6 +322,11 @@ static void ch7xxx_mode_set(struct intel_dvo_device > > *dvo, > > idf |= CH7xxx_IDF_VSP; > > > > ch7xxx_writeb(dvo, CH7xxx_IDF, idf); > > + > > + ch7xxx_writeb(dvo, CH7xxx_DAC_CNTL, > > + CH7xxx_SYNCO_VGA_HSYNC); > > + ch7xxx_writeb(dvo, CH7xxx_CLOCK_OUTPUT, > > + CH7xxx_BCOEN | CH7xxx_BCO_VGA_VSYNC); > > } > > > > /* set the CH7xxx power state */ > > -- > Jani Nikula, Intel Open Source Graphics Center -- Ville Syrjälä Intel
