According to spec, we should check if output_bpp * pixel_rate is less than DDI clock * 72, if UHBR is used.
Signed-off-by: Stanislav Lisovskiy <[email protected]> --- drivers/gpu/drm/i915/display/intel_dp.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index bf80f296a8fdb..13baf3cb5f934 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1582,6 +1582,17 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, drm_dbg_kms(&dev_priv->drm, "DSC: compressed bpp %d slice count %d\n", pipe_config->dsc.compressed_bpp, pipe_config->dsc.slice_count); + + /* wa1406899791 */ + if (intel_dp_is_uhbr(pipe_config)) { + int output_bpp = pipe_config->dsc.compressed_bpp; + + if (output_bpp * adjusted_mode->crtc_clock >= + pipe_config->port_clock * 72) { + drm_dbg_kms(&dev_priv->drm, "DP2 UHBR check failed\n"); + return -EINVAL; + } + } } /* * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate -- 2.37.3
